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d a t a sh eet product speci?cation file under integrated circuits, ic17 1998 nov 02 integrated circuits pca5010 pager baseband controller
1998 nov 02 2 philips semiconductors product speci?cation pager baseband controller pca5010 contents 1 features 2 ordering information 3 general description 4 block diagram 5 pinning information 6 functional description 6.1 general 6.2 cpu timing 6.3 overview on the different clocks used within the pca5010 6.4 memory organization 6.5 addressing 6.6 i/o facilities 6.7 timer/event counters 6.8 i 2 c-bus serial i/o 6.9 serial interface sio0: uart 6.10 76.8 khz oscillator 6.11 clock correction 6.12 6 mhz oscillator 6.13 real-time clock 6.14 wake-up counter 6.15 tone generator 6.16 watchdog timer 6.17 2 or 4-fsk demodulator, filter and clock recovery circuit 6.18 afc-dac 6.19 interrupt system 6.20 idle and power-down operation 6.21 reset 6.22 dc/dc converter 7 instruction set 7.1 instruction map 8 limiting values 9 external components 10 dc characteristics 11 ac characteristics 12 characteristic curves 13 test and application information 14 appendix 1: special modes of the pca5010 14.1 overview 14.2 otp parallel programming mode 14.3 test modes 15 appendix 2: the parallel programming mode 15.1 introduction 15.2 general description 15.3 entering the parallel programming mode 15.4 address space 15.5 single byte programming 15.6 multiple byte programming 15.7 high voltage timing 15.8 otp test modes 15.9 signature bytes 15.10 security 16 appendix 3: os sheet 17 appendix 4: bonding pad locations 18 package outline 19 soldering 19.1 introduction 19.2 reflow soldering 19.3 wave soldering 19.4 repairing soldered joints 20 definitions 21 life support applications 22 purchase of philips i 2 c components
1998 nov 02 3 philips semiconductors product speci?cation pager baseband controller pca5010 1 features operating temperature range: - 10 to +55 c supply voltage range with on-chip dc/dc converter: 0.9 to 1.6 v low operating and standby current consumption on-chip dc/dc converter generates the supply voltage for the pca5010 and external circuitry from a single cell battery battery low detector low electromagnetic noise emission full static asynchronous 80c51 cpu (8-bit cpu) recovery from lowest power standby idle mode to full speed operation within microseconds 32 kbytes of one-time programmable (otp) memory and 1.25 kbyte of ram on-chip 27 general purpose i/o port lines (4 ports with interrupt possibility) 15 different interrupt sources with selectable priority 2 standard timer/event counters t0 and t1 i 2 c-bus serial port (single 100/400 khz master transmitter and receiver) subset of standard uart serial port (8-bit and 9-bit transmission at 4800/9600 bits/s) 76.8 khz crystal oscillator reference with digital clock correction for real time and paging protocol real-time clock (rtc) receiver and synthesizer control C receiver control by software through general purpose i/os C synthesizer control by software through general purpose i/os C 6-bit dac for afc to the receiver local oscillator C dedicated protocol timer. decoding of paging data C pocsag or apoc phase 1; advanced high speed paging protocols are also supported C supported data rates: 1200, 1600, 2400, 3125 and 3200 symbols/s using a 76.8 khz crystal oscillator C demodulation of zero-if i and q, 4 or 2 level fsk input or direct data input C noise filtering of data input and symbol clock reconstruction C de-interleaving, error checking and correction, sync word detection address recognition, buffering and more is performed by software C all user functions (keypad interface, alerter control, display etc.) are implemented in software. musical tone generator for beeper, controlled by the microcontroller watchdog timer 48-pin lqfp package. 2 ordering information note 1. please refer to the order entry form (oef) for this device for the full type number to use when ordering. this type number will also specify the required program. type number (1) product type package name description version PCA5010H/xxx pre-programmed otp lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
1998 nov 02 4 philips semiconductors product speci?cation pager baseband controller pca5010 3 general description the pca5010 pager baseband controller is manufactured in an advanced cmos/otp technology. the pca5010 is an 8-bit microcontroller especially suited for pagers. for this purpose, features such as a 4 or 2 level fsk demodulator, filter, clock recovery, protocol timer, dc/dc converter optimized for small paging systems and rtc are integrated on-chip. the device is optimized for low power consumption. the pca5010 has several software selectable modes for power reduction: idle and power-down mode of the microcontroller and standby and off mode of the dc/dc converter. the instruction set of the pca5010 is based on that of the 80c51. the pca5010 also functions as an arithmetic processor having facilities for both binary and bcd arithmetic plus bit-handling capabilities. the instruction set consists of over 100 instructions: 49 one-byte, 46 two-byte and 16 three-byte. this data sheet details the properties of the pca5010. for details on the i 2 c-bus functions see the i 2 c-bus and how to use it . for details on the basic 80c51 properties and features see data handbook ic20 .
1998 nov 02 5 philips semiconductors product speci?cation pager baseband controller pca5010 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 4 block diagram a ndbook, full pagewidth mgr107 port control p0 v pp p0 xtl2 xtl1 p2 p3 (t0, t1, int0, int1) p1 (sda, scl, rxd, txd) p2 p3 p1 otp/rom timer 0 timer 1 ram processor 80c51 interrupt control uart sio symbol sampling clock recovery digital filter zero-if 4l demodulator i 2 c sio clock correction various clocks clock generator rtc ale, psen, ea tclk wake-up mode and test control power controller tone generator 6 mhz oscillator watchdog dac i(d1), q(d0) afcout at vind v dd(dc) v ss(dc) v bat supplied by v bat v dd v ss resetin resout 76.8 khz oscillator 7 4 8 8 2 2 3 2 dc/dc converter fig.1 block diagram.
1998 nov 02 6 philips semiconductors product speci?cation pager baseband controller pca5010 5 pinning information symbol pin type description p3.4 and p3.5 1 and 2 i/o port 3: p3.4 and p3.5 are con?gured as push-pull outputs only (option 3r, see section 6.6). using the software input commands or the secondary port function is possible by driving the port 3 output lines accordingly: p3.4 secondary function: t0 (counter input for t0) p3.5 secondary function: t1 (counter input for t1) at 3 o beeper high volume control output. used to drive external bipolar transistor. p2.0 to p2.7 4 to 11 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups (option 1s, see section 6.6.3). as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. (see chapter 10: i pu ). port 2 emits the high-order address byte during fetches from external program memory. in this application, it uses strong internal pull-ups when emitting logic 1s. port 2 is also used to control the parallel programming mode of the on-chip otp. p0.0 to p0.4 12 to 16 i/o port 0: port 0 is a bidirectional i/o port with internal pull-ups (option 1s, see section 6.6.3). port 0 pins that have logic 1s written to them are pulled high by the internal pull-ups and can be used as inputs. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-ups when emitting logic 1s. port 0 also outputs the code bytes during otp programming veri?cation. v dda 17 s supply voltage for the analog parts of the pca5010 and the receiver/synthesizer control signals (port 0 pins) afcout 18 o buffered analog output of dac for automatic receiver frequency control. a voltage proportional to the offset of the receiver frequency can be generated. can be enabled/disabled by software. i(d1) 19 i input from receiver: may be demodulated nrz signal or zero-if. in phase limited signal. q(d0) 20 i input from receiver: may be demodulated nrz signal or zero-if. quadrature limited signal. v ssa 21 s ground signal reference (for the analog parts) (connected to substrate) p0.5 to p0.7 22 to 24 i/o port 0: port 0 is a bidirectional i/o port with internal pull-ups (option 1r, 1r, 1s, see section 6.6.3). port 0 pins that have logic 1s written to them are pulled high by the internal pull-ups and can be used as inputs. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-ups when emitting logic 1s. port 0 also outputs the code bytes during otp programming veri?cation. p1.0 to p1.2 25 to 27 i/o port 1: port 1 is an 8-bit quasi bidirectional i/o port with internal pull-ups. port 1 pins that have logic 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see chapter 10: i pu ). p1.0 to p1.2 have external interrupts int2 (x3) to int4 (x5) assigned. p1.3 28 i/o if the uart is disabled (ens1 in s1con.4 = 0) then p1.3 can be used as general purpose p1 port pin. if the uart function is required, then a logic 1 must be written to p1.3. this i/o then becomes the rxd/data line of the uart.
1998 nov 02 7 philips semiconductors product speci?cation pager baseband controller pca5010 p1.4 29 i/o if the uart is disabled (ens1 in s1con.4 = 0) then p1.4 can be used as general purpose p1 port pin. if the uart function is required, then a logic 1 must be written to p1.4. this i/o then becomes the txd/clock line of the uart. p1.4 has external interrupt int6 (x6) assigned. v ss 30 s ground (connected to substrate) v dd 31 s supply voltage for the core logic and most peripheral drivers of the pca5010 (see v dda ) ale 32 i/o address latch enable: output pulse for latching the low byte of the address during an access to external memory. psen 33 i/o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated for each code byte fetch. ea 34 i/o external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 7fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater the 7fffh (32 kbytes). tclk 35 i clock input for use as timing reference in external access mode and emulation v pp 36 s programming voltage (12.5 v) for the otp. is connected to v ss in the application. p1.6 37 i/o if the i 2 c-bus is disabled (ens1 in s1con.6 = 0) then p1.6 can be used as general purpose p1 port pin. if the i 2 c-bus function is required, then a logic 1 must be written to p1.6. this i/o then becomes the clock line of the i 2 c-bus. p1.6 is equipped with an open-drain output buffer. the pin has no clamp diode to v dd . p1.7 38 i/o if the i 2 c-bus is disabled (ens1 in s1con.6 = 0) then p1.7 can be used as general purpose p1 port pin. if the i 2 c-bus function is required, then a logic 1 must be written to p1.7. this i/o then becomes the data line of the i 2 c-bus. p1.7 is equipped with an open-drain output buffer. the pin has no clamp diode to v dd . xtl2 39 o output from the current source oscillator ampli?er xtl1 40 i input to the inverting oscillator ampli?er and time reference for pager decoder, real-time clock and timers v bat 41 s supply terminal from battery. is used for supplying parts of the chip that need to operate at all times. v dd(dc) 42 o supply voltage output of the dc/dc converter. an external capacitor is required. vind 43 i current input for the dc/dc converter. the booster inductor needs to be connected externally. v ss(dc) 44 s ground (connected to substrate) otp resetin 45 i schmitt trigger reset input for the pca5010. external r and c need to be connected to the battery supply. all internal storage elements (except microcontroller ram) are initialized when this input is activated. symbol pin type description
1998 nov 02 8 philips semiconductors product speci?cation pager baseband controller pca5010 resout 46 o monitor output for the emulation system. is active (low) whenever a reset is applied to the microcontroller (a reset can be forced by resetin, watchdog or wake-up from dc/dc converter in off mode). a reset to the microcontroller initializes all sfrs and port pins; it has no impact on the blocks operating from v bat . p3.2 and p3.3 47 and 48 i/o port 3: p3.2 and p3.3 are con?gured as push-pull output only (option 3r, see section 6.6). using the software input commands or the secondary port function is possible by driving the port 3 output lines accordingly: p3.2 secondary function: int0 (external interrupt 0) p3.3 secondary function: int1 (external interrupt 1) symbol pin type description fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 PCA5010H mgr336 v pp tclk ea psen v dd v ss p1.4 p1.3 p1.2 p1.1 p1.0 ale p3.2 resout resetin v ss(dc) vind v dd(dc) xtl1 xtl2 p1.7 p1.6 p3.3 v bat p3.4 p3.5 at p2.0 p2.1 p2.2 p2.4 p2.5 p2.7 p0.0 p2.3 p2.6 p0.2 p0.3 p0.4 v dda afcout i(d1) q(d0) p0.5 p0.6 p0.7 p0.1 v ssa
1998 nov 02 9 philips semiconductors product speci?cation pager baseband controller pca5010 6 functional description 6.1 general the pca5010 contains a high-performance cmos microcontroller and the required peripheral circuitry to implement high-speed pagers for the modern paging protocols. for this purpose, features such as fsk demodulator, protocol timer, real-time clock and dc/dc converter have been integrated on-chip. the microcontroller embedded within the pca5010 implements the standard 80c51 architecture and supports the complete instruction set of the 80c51 with all addressing modes. the pca5010 contains 32 kbytes of otp program memory; 1.25 kbyte of static read/write data memory, 27 i/o lines, two 16-bit timer/event counters, a fifteen-source two priority-level, nested interrupt structure and on-chip oscillator and timing circuit. the pca5010 devices have several software selectable modes of reduced activity for power reduction; idle for the cpu and standby or off for the dc/dc converter. the idle mode freezes the cpu while allowing the ram, timers, serial i/o and interrupt system to continue functioning. the standby mode for the dc/dc converter allows a high efficiency of the latter at low currents and the off mode reduces the supply voltage to the battery level. in the off mode the ram contents are preserved, real-time clock and protocol timer are operating, but all other chip functions are inoperative. two serial interfaces are provided on-chip; a uart serial interface and an i 2 c-bus serial interface. the i 2 c-bus serial interface has byte oriented master functions allowing communication with a whole family of i 2 c-bus compatible slave devices. 6.2 cpu timing the internal cpu timing of the pca5010 is completely different to other implementations of this core. the cpu is realized in asynchronous handshaking technology, which results in extremely low power consumption and low emc noise generation. 6.2.1 b asics the implementation of the cpu of the pca5010 as a block in handshake technology has become possible through the tangram tool set, developed in the philips natlab in eindhoven. tangram is a high level programming language which allows the description of parallel and sequential processes that can be compiled into logic on silicon. the cpu has the following features: no clock is needed. every function within the cpu is self timed and always runs at the maximum speed that a given silicon die under the current operating conditions (supply voltage and temperature) allows. the cpu fetches opcodes with maximum speed until a special mode (e.g. idle) is entered that stops this sequence. only bytes that are required are fetched from the program memory. the dummy read cycles which exist in the standard 80c51 have been omitted to save power. to further speed up the execution of a program, the next sequential byte is always fetched from the code memory during the execution of the current command. in the event of jumps the prefetched byte is discarded. since no clocks are required, the operating power consumption is essentially lower compared to conventional architectures and idle power consumption is reduced to nearly zero (leakage only). clocks are only required as timing references for timers/counters and for generating the timing to the off-chip world. 6.2.2 e xecution of programs from internal code memory when code is executed in internal access mode ( ea = 1), the opcodes are fetched from the on-chip otp. the otp is a self timed block which delivers data at maximum speed. this is the preferred operating mode of the pca5010. 6.2.3 e xecution of programs from external code memory when code is executed in external access mode ( ea = 0), the opcodes are fetched from an off-chip memory using the standard signals ale, psen and p0, p2 for multiplexed data and address information. in this mode the identical hardware configurations as for a standard 80c51 system can be used, even if the timing for ale and psen is slightly different because it is generated from an internal oscillator.
1998 nov 02 10 philips semiconductors product speci?cation pager baseband controller pca5010 6.3 overview on the different clocks used within the pca5010 figure 3 gives an overview on the clocks available within the pca5010 for the different functions. fig.3 overview on the clocks used within the pca5010. handbook, full pagewidth mgl460 timer 1 (both clock edges are used) demodulator/ clock recovery microcontroller output and external access timer 0 real-time clock watchdog wake-up counter dc/dc converter i 2 c-bus uart (both clock edges are used) tone generator (both clock edges are used) 76.8 khz 76.8 khz 76.8 khz 76.8 khz 256 hz 4 hz 16 hz 9.6 khz 6 mhz 76.8 khz 1.5 mhz 6 mhz divider for the different frequencies 150 9600 2400 4 divider 38.4 khz corr clock correction 76.8 khz oscillator ccon.7 6 mhz oscillator os6con.7 os6con.7
1998 nov 02 11 philips semiconductors product speci?cation pager baseband controller pca5010 6.4 memory organization the pca5010 has a program memory (otp) plus data memory (ram) on-chip. the device has separate address spaces for program and data memory (see fig.4). if ports p0 and p2 are not used as i/o signals these pins can be used to address up to 64 kbytes of external program memory. in this case, the cpu generates the latch signal (ale) for an external address latch and the read strobe ( psen) for external program memory. external data memory is not supported. 6.4.1 p rogram memory after reset the cpu begins execution of the program memory at location 0000h. the program memory can be implemented in either internal otp or external memory. if the ea pin is strapped to v dd , then program memory fetches are directed to the internal program memory. if the ea pin is strapped to v ss , then program memory fetches are directed to external memory. programming the on-chip otp is detailed in chapter 15. usually philips will deliver programmed parts to a customer. supply of blank engineering samples is possible, but then philips cannot give any guarantee on the programmability and retention of the program memory. 6.4.2 d ata memory the pca5010 contains 1280 bytes internal ram (consisting of 256 bytes standard ram and 1024 bytes aux-ram) and special function registers (sfrs). figure 4 shows the internal data memory space divided into the lower 128 bytes the upper 128 bytes and the sfr space and 1024 bytes auxiliary ram. internal ram locations 0 to 127 are directly and indirectly addressable. internal ram locations 128 to 255 are only indirectly addressable. the sfr locations 128 to 255 bytes are only directly addressable and the auxiliary ram is indirectly addressable as external ram (movx). external data memory (edm) is not supported. 6.4.3 s pecial function registers the second 128 bytes are the address locations of the special function registers. table 1 shows the special function registers space. the sfrs include the port latches, timers, peripheral control, serial i/o registers, etc. these registers can only be accessed by direct addressing. there are 128 bit addressable locations in the sfr address space (those sfrs whose addresses are divisible by eight). fig.4 memory map. handbook, full pagewidth mgl459 internal ram indirect and direct addressing sfr space external xram is not supported external (ean = 0) internal (ean = 1) external indirect addressing direct addressing internal xram indirect addressing with dptr indirect addressing with ri, dptr ffh 00h 0 7fh 80h 3ffh 000h 0ffh 100h data memory program memory 7fffh ffffh
1998 nov 02 12 philips semiconductors product speci?cation pager baseband controller pca5010 6.5 addressing the pca5010 has five methods for addressing source operands: register direct register-indirect immediate base-register plus index-register-indirect. the first three methods can be used for addressing destination operands. most instructions have a destination/source field that specifies the data type, addressing methods and operands involved. for operations other than movs, the destination operand is also a source operand. access to memory addressing is as follows: registers in one of the four 8-register banks through register direct or register-indirect maximum 1280 bytes of internal data ram through direct or register-indirect C bytes 0 to 127 of internal ram may be addressed directly/indirectly. bytes 128 to 255 of internal ram share their address location with the sfrs and so may only be addressed register-indirect as data ram. C bytes 0 to 1024 of aux-ram can be addressed indirectly via movx. bytes 256 to 1024 can only be addressed using indirect addressing with the data pointer, while bytes 0 to 255 may be also addressed using r0 or r1. special function registers through direct program memory look-up tables (luts) through base-register plus index-register-indirect. the pca5010 is classified as an 8-bit device since the internal rom, ram, special function registers (sfrs), arithmetic logic unit (alu) and external data bus are all 8-bits wide. it performs operations on bit, nibble, byte and double-byte data types. facilities are available for byte transfer, logic and integer arithmetic operations. data transfer, logic and conditional branch operations can be performed directly on boolean variables to provide excellent bit handling. while the pca5010 is executing code from the internal memory, ale and psen pins are inactive with ale = low and psen = high. external xram is not supported for this device, since p3.7 ( rd) and p3.6 ( wr) pins are not available. if the external xram is accessed accidentally, no psen or ale cycle is done and actual p0 values are read. internal xram access is not visible from outside the chip (no ale, psen, p0 and p2 activity).
1998 nov 02 13 philips semiconductors product speci?cation pager baseband controller pca5010 table 1 special function registers overview; note 1 addr (hex) name 7 6 5 4 3 2 1 0 r/w reset value comment 80 p0 rw 9fh bit addressable 81 sp rw 07h 82 dpl rw 00h 83 dph rw 00h 87 pcon smod xre enis - gf1 gf0 pd idl rw 00h 88 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 rw 00h bit addressable 89 tmod gate c/t m1 m0 gate c/t m1 m0 rw 00h 8a tl0 rw 00h 8b tl1 rw 00h 8c th0 rw 00h 8d th1 rw 00h 90 p1 rw ffh bit addressable 92 tgcon enb clk2 ---- - - rw 00h 93 tg0 rw 00h 94 wucon run wup test cpl z1 z0 load set rw 00h see note 2 95 wuc0 rw 00h see note 2 96 wuc1 rw 00h see note 2 98 s0con sm0 sm1 - ren tb8 rb8 ti ri rw 00h bit addressable 99 s0buf rw 00h 9e afcon enb - afc5 afc4 afc3 afc2 afc1 afc0 rw 00h a0 p2 rw ffh bit addressable a5 wdcon cond wd3 wd2 wd1 wd0 -- ld rw 00h a8 ien0/ie ea ewu es1 es0 et1 ex1 et0 ex0 rw 00h bit addressable b0 p3 rw c3h bit addressable b8 ip/ip0 - pwu ps1 ps0 pt1 px1 pt0 px0 rw 00h bit addressable c0 irq1 iq9 iq8 iq7 iq6 iq5 iq4 iq3 iq2 rw 00h bit addressable cd rtcon min ---- w/ r load set rw 00h see note 2 ce rtc0 rw 00h see note 2 d0 psw cy ac f0 rs1 rs0 ov p (3) rw 00h bit addressable d1 dccon0 off sby rxe sbli -- stb (3) bli (3) rw 03h d2 dccon1 vbg1 vbg0 vlo1 vlo0 ---- rw 00h d3 os6con enb - sf4 sf3 sf2 sf1 sf0 mfr rw 00h d4 os6m0 r 00h d8 s1con - ens1 sta sto si aa - cr0 rw 00h bit addressable d9 s1sta sc4 sc3 sc2 sc1 sc0 0 0 0 r 78h da s1dat rw 00h e0 acc rw 00h bit addressable e8 ien1 emin ewd edc ex6 esc ex4 ex3 ex2 rw 00h bit addressable e9 ix1 il9 il8 il7 il6 il5 il4 il3 il2 rw 00h
1998 nov 02 14 philips semiconductors product speci?cation pager baseband controller pca5010 notes 1. an empty field in this map indicates a bit that can be read or written to by software. 2. value only reset with resetin and not or only partly with an off-restart sequence. 3. this bit cannot be changed by writing to it. ec dmd0 enb m - res lev bd2 bd1 bd0 rw 00h ed dmd1 ena avg6 avg5 avg4 avg3 avg2 avg1 avg0 r 00h ena is rw ee dmd2 enc - bf - test b2 b1 b0 rw 00h ef dmd3 rw 00h f0 b rw 00h bit addressable f8 ip1 pmin pwd pdc px6 psc px4 px3 px2 rw 00h bit addressable fc ccon enb plus test civ17 civ16 - bypas set rw 00h fd cc0 civ7 civ6 civ5 civ4 civ3 civ2 civ1 civ0 rw 00h fe cc1 civ15 civ14 civ13 civ12 civ11 civ10 civ9 civ8 rw 00h addr (hex) name 7 6 5 4 3 2 1 0 r/w reset value comment fig.5 the lower 128 bytes of internal data memory. handbook, halfpage mla560 - 1 r7 r0 07h 0 r7 r0 0fh 08h r7 r0 17h 10h r7 r0 1fh 18h 2fh 7fh 20h 30h bit-addressable space (bit addresses 0 to 7f) 4 banks of 8 registers (r0 to r7)
1998 nov 02 15 philips semiconductors product speci?cation pager baseband controller pca5010 6.6 i/o facilities 6.6.1 p orts the pca5010 has 27 i/o lines treated as 27 individually addressable bits or as four parallel 8-bit addressable ports. ports 0 and 2 are complete, port 1 has only 7 and port 3 has only 4 pins externally available. ports 0, 1, 2 and 3 perform the following alternative functions: port 0 is also used for external access, parallel otp programming mode and emulation (see table 2 for configuration details): provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals provides access to the otp data i/o lines in otp parallel programming mode. port 1 used for a number of alternative functions (see table 3 for configuration details): provides the inputs for the external interrupts int2/p1.0 to int4/p1.2 and int6/p1.4 scl/p1.6 and sda/p1.7 for the i 2 c-bus interface are real open-drain outputs; no other port configurations are available rxd/p1.3 and txd/p1.4 for the uart data input and output. port 2 is also used for external access, parallel otp programming mode and emulation (see table 4 for configuration details): provides the high-order address bus when expanding the device with external program memory allows control of the on-chip otp parallel programming mode. port 3 pins are configured as strong push-pull outputs (see table 5 for configuration details). the following alternative port 3 functions are available, but to avoid short-circuiting of the mentioned port pins, the input signals cannot be applied externally to the port 3 pins. the alternative function can only be stimulated via the respective port output function: external interrupt request inputs int0/p3.2 and int1/p3.3 counter inputs t0/p3.4 and t1/p3.5. to enable a port pin alternative function, the port bit latch in its sfr must contain a logic 1. each port consists of a latch (sfrs p0 to p3), an output driver and input buffer. standard ports have internal pull-ups. figure 6a shows that the strong transistor p1 is turned on for only a short time after a low-to-high transition in the port latch. when on, it turns on p3 (a weak pull-up) through the inverter in1. this inverter and p3 form a latch which holds the logic 1. 6.6.2 p ort i/o configuration ( options ) i/o port output configurations are determined on-chip according to one of the options shown in fig.6. they cannot be changed by software.
1998 nov 02 16 philips semiconductors product speci?cation pager baseband controller pca5010 fig.6 port configuration options. a. standard/quasi-bidirectional (option 1). b. push-pull (option 3). c. open-drain (only sda/p1.7, scl/p1.6) (option 2). handbook, full pagewidth mgr111 v ss v dd v ss i/o pin strong pull-up delay >50 ns n in1 p1 p2 p3 q from port latch weak pull-up hold pull-up input data handbook, full pagewidth mgr112 v ss v dd v dd v ss i/o pin strong pull-up n p1 q from port latch input data handbook, full pagewidth mgr113 low-pass filter slew rate control v ss v ss v dd external i/o pin input data external pull-up q from port latch n
1998 nov 02 17 philips semiconductors product speci?cation pager baseband controller pca5010 6.6.3 p ort i/o configuration tables 2 to 6 show the hardwired configuration for the different i/os of the pca5010. table 2 port 0 con?guration; notes 1 and 2 notes 1. option 1s means port configuration option 1 with post-reset state set to high; option 1r means post-reset state will be low. 2. hys means input stage with hysteresis. table 3 port 1 con?guration table 4 port 2 con?guration port pin configuration pull-up input reset drive possible application in a pager p0.0 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_enable (o) p0.1 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma spi_enable (o) p0.2 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma spi_clock (o) p0.3 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma spi_data (o) p0.4 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma spi_data (i) p0.5 quasi bidirectional i/o (option 1r) yes hys low 0.75 ma rxe (o) p0.6 quasi bidirectional i/o (option 1r) yes hys low 0.75 ma roe (o) p0.7 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma bandwidth (o)/rssi (i) port pin configuration pull-up input reset drive possible application in a pager p1.0 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma key p1.1 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma key p1.2 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma key p1.3 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma rxd p1.4 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma txd p1.5 not available p1.6 i 2 c-bus open-drain i/o (option 2s) (slew rate limited) no hys high 2.25 ma scl p1.7 i 2 c-bus open-drain i/o (option 2s) (slew rate limited) no hys high 2.25 ma sda port pin configuration pull-up input reset drive possible application in a pager p2.0 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data p2.1 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data p2.2 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data p2.3 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data
1998 nov 02 18 philips semiconductors product speci?cation pager baseband controller pca5010 table 5 port 3 con?guration the port configuration is fixed and cannot be reconfigured by software or otp code. table 6 other pins p2.4 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data p2.5 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data p2.6 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data p2.7 quasi bidirectional i/o (option 1s) yes hys high 0.75 ma lcd_data port pin configuration pull-up input reset drive possible application in a pager p3.0 not available p3.1 not available p3.2 push-pull output (option 3r) no hys low 3 ma call led p3.3 push-pull output (option 3r) no hys low 3 ma vibrator p3.4 push-pull output (option 3r) no hys low 3 ma back light p3.5 push-pull output (option 3r) no hys low 3 ma lcd r/ w/rxd enable p3.6 not available p3.7 not available port pin configuration pull-up input reset drive possible application in a pager at push-pull output no low 3 ma tone generator output i(d1) digital input no hys q(d0) digital input no hys tclk digital input no hys resetin digital input no hys reset input resout push-pull output no low 1.5 ma reset output xtl1 analog input/output (10 pf) no hys to crystal quartz xtl2 analog input/output (10 pf) no to crystal quartz afcout analog output no ale quasi bidirectional i/o yes hys high 1.5 ma psen quasi bidirectional i/o yes hys high 0.75 ma ea 3-state i/o with bus keeper hold buffer high 0.75 ma port pin configuration pull-up input reset drive possible application in a pager
1998 nov 02 19 philips semiconductors product speci?cation pager baseband controller pca5010 6.7 timer/event counters the pca5010 contains two 16-bit timer/event counters: timer 0 and timer 1 which can perform the following functions: measure time intervals and pulse durations count events generate interrupt requests generate output on comparator match generate a pulse width modulated (pwm) output signal. timer 0 and timer 1 can be programmed independently to operate in four modes: mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. mode 1 16-bit time interval or event counter. mode 2 8-bit time interval or event counter with automatic reload upon overflow. mode 3 this mode of the standard 80c51 is not available. in the timer mode the timers count events on the xtl1 input. timer 0 counts through a prescaler at a rate of 256 hz and timer 1 counts directly on both edges of the xtl1 signal at a rate of 153.6 khz. the nominal frequency of the xtl1 signal is 76.8 khz. in the counter mode the register is incremented in response to a high-to-low transition at p3.4 (t0) and p3.5 (t1). besides the different input frequencies and the non-availability of mode 3, both timer 0 and timer 1 behave exactly identical to the standard 80c51 timer 0 and timer 1. fig.7 timer/counter 0 and 1: clock sources and control logic. handbook, full pagewidth mgr114 153.6 khz c/t = 0 c/t = 1 tl1 th1 300 256 hz c/t = 0 c/t = 1 tl0 xtl1 t0 tr0 gate int0 xtl1 t1 tr1 gate int1 th0 detailed configuration of the 4 available modes is found in the 80c51 family hardware description ( philips semiconductors ic20 data handbook ).
1998 nov 02 20 philips semiconductors product speci?cation pager baseband controller pca5010 6.8 i 2 c-bus serial i/o the serial port supports the 2-line i 2 c-bus which consists of a data line (sda) and a clock line (scl). these lines also function as the i/o port lines p1.7 and p1.6 respectively. the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling. the implementation in the pca5010 operates in single master mode as: master transmitter master receiver. these functions are controlled by the s1con register. s1sta is the status register whose contents may also be used as a vector to various service routines. s1dat is the data shift register. the block diagram of the i 2 c-bus serial i/o is shown in fig.8. 6.8.1 d ifferences to a standard i 2 c- bus interface the i 2 c-bus interface of the pca5010 implements the standard for master receiver and transmitter as defined in e.g. p83cl781/782 with the following restrictions: the baud rate is fixed to either 100 khz (cr0 = 0) or 400 khz (cr0 = 1) derived from the on-chip 6 mhz oscillator. therefore bits cr1 and cr2 in the s1con sfr are not available. only single master functions are implemented. C slave address (s1adr) is not available C status register (s1sta) reports only status defined for the mst/trx and mst/rec modes C multimaster operation is not supported. fig.8 block diagram of i 2 c-bus serial i/o. handbook, full pagewidth mgl449 shift register s1dat sda arbitration logic scl bus clock generator s1sta internal bus 76543210 s1con 76543210
1998 nov 02 21 philips semiconductors product speci?cation pager baseband controller pca5010 6.8.2 t iming the timing of the i 2 c-bus interface is based on the internal 6 mhz clock. the phases of this clock divided-by-4 are used as a reference in the 400 khz mode and divided-by-16 in the 100 khz mode. in the following context t (333 ns or 1.33 m s) denotes a single phase of this clock. the transfer of a single bit lasts 9 t. scl is high for 5 t. when receiving data, the pca5010 samples the sda line after 3 t while scl is high. the implemented i 2 c-bus interface operates according to the timing diagram in fig.9. the open-drain i 2 c-bus outputs are implemented as slew rate controlled driver stages, to minimize the negative impact of i 2 c-bus activity on the pager sensitivity while the pager is receiving. typical waveforms on p1.7 (sda) and p1.6 (scl) are shown in fig.10. because sda and scl are open-drain type i/os, only the falling edge is determined by the driver characteristics. the static sink current when driving low and the slope of the rising edges are determined by the capacitive i 2 c-bus load and its resistive termination (pull-up to v dd ). fig.9 timing of the i 2 c-bus interface. handbook, full pagewidth mgr337 3t 4t start scl sda stop 5t 2t 2t 2t tx bit 2t 2t 5t 2t 2t 3t 2t rx bit
1998 nov 02 22 philips semiconductors product speci?cation pager baseband controller pca5010 6.8.3 s erial c ontrol r egister (s1con) table 7 serial control register (s1con, sfr address d8h) 76543210 - ens1 sta sto si aa - cr0 fig.10 typical waveforms on sda and scl. (1) the falling slope depends on the capacitive load. typical values at 2.2 v where c l = 50 pf are: t f = 100 ns; i sw = 2 ma; dl/dt = 250 m a/ns. (2) the rising slope is defined by external pull-up resistor and capacitive load (a typical t r is 1 m s at 50 pf/20 k w . handbook, full pagewidth mgr338 voltage (sda, scl) sink current (sda, scl) (1) (2) i pu t f t r i sw dl/dt v dd v ss
1998 nov 02 23 philips semiconductors product speci?cation pager baseband controller pca5010 table 8 description of the s1con bits 6.8.4 d ata s hift r egister (s1dat) s1dat contains the serial data to be transmitted or data which has just been received. bit 7 is transmitted or received first; i.e. data shifted from left to right. table 9 data shift register (s1dat, sfr address dah) 6.8.5 a ddress r egister (s1adr) the slave address register is not available since slave mode is not supported. bit symbol function s1con.7 - cr2 is not available. s1con.6 ens1 enable serial i/o . when ens1 = 0, the serial i/o is disabled. sda and scl outputs are in the high-impedance state; p1.6 and p1.7 function as open-drain ports. when ens1 = 1, the serial i/o is enabled. output port latches p1.6 and p1.7 must be set to logic 1. s1con.5 sta start ?ag . if sta is set while the sio is in master mode, sio will generate a repeated start condition. s1con.4 sto stop ?ag . with this bit set while in master mode a stop condition is generated. when a stop condition is detected on the i 2 c-bus, the sio hardware clears the sto ?ag. s1con.3 si sio interrupt ?ag . this ?ag is set, and an interrupt is generated, after any of the following events occur: a start condition is generated in master mode a data byte has been received or transmitted in master mode (even if arbitration is lost). if this ?ag is set, the i 2 c-bus is halted (by pulling down scl). received data is only valid until this ?ag is reset. s1con.2 aa assert acknowledge . when this bit is set, an acknowledge (low level to sda) is returned during the acknowledge clock pulse on the scl line when: a data byte is received while the device is programmed to be a master receiver. when this bit is reset, no acknowledge is returned. s1con.1 - cr1 is not available. s1con.0 cr0 speed selection (with on-chip 6 mhz oscillator tuned to 6 mhz the nominal bus frequency is: cr0 = 0 is 83.3 khz (6 mhz divided-by-72) cr0 = 1 is 333 khz (6 mhz divided-by-18). 76543210 d7 d6 d5 d4 d3 d2 d1 d0
1998 nov 02 24 philips semiconductors product speci?cation pager baseband controller pca5010 6.8.6 s erial s tatus r egister (s1sta) the contents of this register may be used as a vector to a service routine. this optimizes the response time of the software and consequently that of the i 2 c-bus. s1sta is a read-only register. the status codes for all available modes of a single master i 2 c-bus interface are given in tables 12 to 14. table 10 serial status register (s1sta and sfr address d9h) table 11 description of the s1sta bits table 12 mst/trx mode table 13 mst/rec mode table 14 miscellaneous 76543210 sc4 sc3 sc2 sc1 sc0 0 0 0 bit symbol function s1sta.3 to s1sta.7 sc4 to sc0 5-bit status code s1sta.0 to s1sta.2 - these 3 bits are held low s1sta value description 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 18h sla and w have been transmitted, ack has been received 20h sla and w have been transmitted, ack received 28h data of s1dat has been transmitted, ack received 30h data of s1dat has been transmitted, ack received s1sta value description 40h sla and r have been transmitted, ack received 48h sla and r have been transmitted, ack received 50h data has been received, ack returned 58h data has been received, ack returned s1sta value description 78h no information available (reset value); the serial interrupt ?ag si, is not yet set
1998 nov 02 25 philips semiconductors product speci?cation pager baseband controller pca5010 table 15 symbols used in tables 12 to 14 symbol description sla 7-bit slave address r read bit w write bit ack acknowledgement (acknowledge bit = logic 0) ack no acknowledgement (acknowledge bit = logic 1) data 8-bit data byte to or from i 2 c-bus mst master slv slave trx transmitter rec receiver 6.9 serial interface sio0: uart the uart interface of the pca5010 implements a subset of the complete standard as defined in e.g. the p80cl580. 6.9.1 d ifferences to the standard 80c51 uart the following deviations from the standard exist: if [sm1 and sm0] = 10 then mode 1 (8-bit data transmission) is selected, with a fixed baud rate (4800/9600 bits/s) if [sm1 and sm0] = 01 then mode 2 (9-bit data transmission) is selected, with a fixed baud rate (4800/9600 bits/s) modes 0 and 3 and the variable baud rate selection using timer 1 overflow is not available the sm2 bit has no function the time reference for modes 1 and 2 is taken from the 76.8 khz oscillator, instead of the original 6.9.2 uart modes this serial port is full duplex which means that it can transmit and receive simultaneously. it is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. however, if the first byte has not been read by the time the reception of the second byte is complete, the second byte will be lost. the serial port receive and transmit registers are both accessed via the special function register s0buf. writing to s0buf loads the transmit register and reading s0buf accesses a physically separate receive register. f osc 12 ----------- the serial port can operate in 2 modes: mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first) and a stop bit (1). on receive, the stop bit goes into rb8 in special function register s0con (see figs 11 and 12). mode 2 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit and a stop bit (1). on transmit, the 9th data bit (tb8 in s0con) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in s0con, while the stop bit is ignored (see figs 11 and 13). in both modes the baud rate can be selected to either 4800 or 9600 depending on the smod bit in the pcon sfr. if smod = 0 the baud rate is 4800, if smod = 1 the baud rate is 9600 with a 76.8 khz quartz. in both modes, transmission is initiated by any instruction that uses s0buf as a destination register. reception is initiated by the incoming start bit if ren = 1. 6.9.3 s erial p ort c ontrol r egister (s0con) the serial port control and status register is the special function register s0con (see table 16). the register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri).
1998 nov 02 26 philips semiconductors product speci?cation pager baseband controller pca5010 table 16 serial port control register (s0con, sfr address 98h) table 17 description of the s0con bits table 18 selection of the serial port modes 6.9.4 uart data register (s0buf) s0buf contains the serial data to be transmitted or data which has just been received. bit 0 is transmitted or received first. table 19 data shift register (s0buf, sfr address 99h) 6.9.5 b aud rates the baud rate in modes 1 and 2 depends on the value of the smod bit in sfr pcon and may be calculated as: if smod = 0, (which is the value on reset), the baud rate is 1 16 f osc if smod = 1, the baud rate is 1 8 f osc . 76543210 sm0 sm1 - ren tb8 rb8 ti ri bit symbol function s0con.7 sm0 this bit along with the sm1 bit, is used to select the serial port mode; see table 18 s0con.6 sm1 this bit along with the sm0 bit, is used to select the serial port mode; see table 18 s0con.5 - sm2 is not available s0con.4 ren this bit enables serial reception and is set by software to enable reception, and cleared by software to disable reception s0con.3 tb8 this bit is the 9th data bit that will be transmitted in mode 2; set or cleared by software as desired s0con.2 rb8 in mode 2, this bit is the 9th data bit received; in mode 1 it is the stop bit that was received s0con.1 ti the transmit interrupt ?ag . set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. must be cleared by software. s0con.0 ri the receive interrupt ?ag . set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (for exception see sm2). must be cleared by software. sm0 sm1 mode description baud rate 0 1 1 8-bit uart 1 16 f osc or 1 8 f osc 1 0 2 9-bit uart 1 16 f osc or 1 8 f osc 76543210 d7 d6 d5 d4 d3 d2 d1 d0 baud rate 2 smod 16 ---------------- - f osc =
1998 nov 02 27 philips semiconductors product speci?cation pager baseband controller pca5010 fig.11 serial port mode 1 and mode 2. handbook, full pagewidth mgl452 start stop bit shift data t1 tx control tx clock send 8 serial port interrupt 8 rx clock r1 load sbuf shift rx control start sample input shift register (9-bits) bit detector s0 buffer internal bus read sbuf shift load sbuf s0 buffer zero detector shift d cl s q tb8 internal bus write to sbuf 2 xtl1 rxd txd 0 csmod at pcon.7 1 high-to-low transition detector
1998 nov 02 28 philips semiconductors product speci?cation pager baseband controller pca5010 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mgl451 d0 d1 d2 d3 d4 d5 d6 d7 start bit d0 d1 d2 d3 d4 d5 d6 d7 tx clock write to sbuf data shift txd ti start bit stop bit 8 reset rx clock rxd stop bit bit detector sample time shift ri send t r a n s m i t r e c e i v e fig.12 serial port mode 1 timing.
1998 nov 02 29 philips semiconductors product speci?cation pager baseband controller pca5010 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.13 serial port mode 2 timing. handbook, full pagewidth tx clock stop bit gen rx clock bit detector sample time shift mgl450 d0 d1 d2 d3 d4 d5 d6 d7 tb8 write to sbuf send data shift txd ti start bit stop bit 8 reset start bit rxd d0 d1 d2 d3 d4 d5 d6 d7 stop bit ri rb8 t r a n s m i t r e c e i v e
1998 nov 02 30 philips semiconductors product speci?cation pager baseband controller pca5010 6.10 76.8 khz oscillator 6.10.1 f unction the oscillator produces a reference frequency of 76.8 khz. the frequency offset is compensated by a separate digital clock correction block. the oscillator operates directly on v bat and is always enabled. 6.10.2 o scillator circuitry the on-chip inverting oscillator amplifier is a single nmos transistor supplied with a constant current. the amplitude visible at terminals xtl1 and xtl2 is therefore not a full rail swing with a very high impedance. to reduce the power consumption, the input schmitt trigger buffer is limited to approximately 100 khz maximum frequency. the whole circuit operates directly at the battery supply. the 76.8 khz oscillator cannot be disabled. it also continues its operation during dc/dc converter off or 80c51 stop mode. the simplest application configuration is shown in fig.14a. c1 and c2 can be added to operate a crystal at its optimal load condition. the resulting capacitance of the series connection of c1 and c2 must be smaller than 5 pf for a guaranteed start-up of the oscillator. fig.14 oscillator circuit. handbook, full pagewidth mgr115 2 m w 76.8 khz 10 pf (a) (b) (c) 10 pf 76.8 khz 76.8 khz 76.8 khz xtl1 xtl2 76.8 khz 10 pf 10 pf xtl1 xtl2 2 m w c1 v p = v bat f max = 100 khz c2 10 pf 10 pf xtl1 xtl2
1998 nov 02 31 philips semiconductors product speci?cation pager baseband controller pca5010 6.11 clock correction 6.11.1 f unction the clock correction block is connected to the 76.8 khz oscillator. it operates directly on v bat . by means of the clock correction circuit a digital adjustment of the 76.8 khz oscillator signal is implemented. an 18-bit interval counter inserts or deletes one pulse from the 76.8 khz clock each time its count has expired. the interval is stored by the processor to the 18-bit interval register civ. addition/deletion is performed by hardware. crystal offset correction can be performed with a resolution of 5 ppm. this block also generates the timing reference signals for other functional blocks such as the rtc (4 hz), watchdog (16 hz), timer 0 (256 hz), wake-up counter (9600 hz) and the demodulator/clock recovery block. the generation of these timing references is always active and cannot be disabled. fig.15 block diagram of clock compensation. handbook, full pagewidth mgr116 qd q r d 1 store 76.8 khz corrected 38.4 khz internal set flag sfr to microcontroller reset with each off cycle set enb plus bypass test civ0 to civ17 interval latch (18-bit) reload data interval counter (18-bit) (reload on carry) & v dd supply reset only on resetin carry add/delete one pulse on carry 2 v bat supply
1998 nov 02 32 philips semiconductors product speci?cation pager baseband controller pca5010 6.11.2 c lock c orrection c ontrol r egister (ccon) the ccon special function register is used to control the clock correction by software. table 20 clock correction control register (ccon, sfr address fch) table 21 description of the ccon bits 6.11.3 c lock c orrection i nterval r egisters (cc0 and cc1) the cc0 and cc1 special function registers (together with ccon.3 and ccon.4) are used to define the interval between subsequent clock correction actions. table 22 clock correction interval register (cc0, sfr address fdh) table 23 clock correction interval register (cc1, sfr address feh) 76543210 enb plus test civ17 civ16 - bypass set bit symbol function ccon.7 enb enable clock correction . if enb = 1 has been set, then correction is enabled and will stay enabled even when the dc/dc converter is shut down and restarted. ccon.6 plus sign for value . if plus = 1 then clock pulses are inserted, or else deleted. ccon.5 test test signal , must always be logic 0 in normal mode. it is used during test to bypass the ?rst 9 ffs in the timing generator divider chain. if test = 1 the clock rate of the signals 9600 hz and 256 hz is doubled and the frequency on 16 hz and 4 hz is multiplied by 300. ccon.4 civ17 bit 17 of interval value, is used as extension of cc0 and cc1 ccon.3 civ16 bit 16 of interval value, is used as extension of cc0 and cc1 ccon.2 - unused. ccon.1 bypass test signal , must always be logic 0 in normal mode. it is used during test to generate 76.8 khz on all outputs of the timing generator (4 hz, 16 hz, 256 hz and 9600 hz). ccon.0 set a load signal to the interval register . after a logic 0 to logic 1 transition of this bit the value of enb, plus, test, bypass and civ are copied into the local latches with the next 76.8 khz clock pulse. a duration of one mov instruction is long enough for the set operation to complete. the sfr values must remain stable for at least one oscillator period because the actual transfer happens synchronized with the local clock (see figs 16 and 18). 76543210 civ7 civ6 civ5 civ4 civ3 civ2 civ1 civ0 76543210 civ15 civ14 civ13 civ12 civ11 civ10 civ9 civ8
1998 nov 02 33 philips semiconductors product speci?cation pager baseband controller pca5010 6.11.4 e xample sequence to set another clock correction interval fig.16 sequence for setting the clock compensation. handbook, full pagewidth mgr117 plus, enb and civ set valid value in sfr must stay valid for one period of 76.8 khz mov cc0, #(civ7 to civ0) mov cc1, #(civ8 to civ15) mov ccon, #d4h mov ccon, #d5h. 6.11.5 t iming figures 17 and 18 demonstrate how the clock correction works and how the access of the microcontroller is synchronized to the local operation. fig.17 operation of clock compensation. handbook, full pagewidth mgr118 [civ] - 5 [civ] - 4 [civ] - 3 [civ] - 2 [civ] - 1 [civ] 0 1 2 3 4 5 6 7 [civ] - 5 [civ] - 4 [civ] - 3 [civ] - 2 [civ] - 1 [civ] 0 1 2 3 4 5 6 interval counter corr for clock recovery corrected 38.4 khz with plus = 1 corrected 38.4 khz with plus = 0 76.8 khz 38.4 khz after (civ) clock ticks of 76.8 khz or 38.4 khz one correction is made.
1998 nov 02 34 philips semiconductors product speci?cation pager baseband controller pca5010 fig.18 synchronization of local counter operation and access from the microcontroller. handbook, full pagewidth mgr119 set (sfr) 76.8 khz set flag (local) store (local) data (sfr) data (local) counter reload from local data i i - 1 i - 2 i - 3 i - 4 1 0 k k - 1 k - 2 k k 6.12 6 mhz oscillator 6.12.1 f unction the 6 mhz oscillator provides the clock for the dc/dc converter, the i 2 c-bus interface, the port i/os and for the external memory access timing (ale/ psen). the 6 mhz oscillator is a 5 inverter stage current controlled ring oscillator. the oscillator is optimized for low operating current consumption. the actual frequency of the oscillator can be measured by activating the mfr signal. an 8-bit counter will then be reset and will start counting at the first rising edge of the 76.8 khz signal and stop counting at the next rising edge of the 76.8 khz signal. the processor then can read the contents of the mfr counter. the processor can adjust the oscillator frequency using the f0 to f4 signals (control of source current for ring oscillator). the 6 mhz oscillator is enabled by hardware only during the start-up phase and whenever the dc/dc converter needs the 6 mhz clock. in all other cases the 6 mhz oscillator is switched of by hardware. the dc/dc converter does not need the 6 mhz clock when set in standby mode. if the 6 mhz output is required as a frequency source for other blocks (e.g. i 2 c-bus) the software needs to enable it explicitly by setting enb = 1. besides the dc/dc converter the following functions require the operation of the 6 mhz oscillator: i 2 c-bus block as basic time reference port output logic. software commands that write to the ports need this clock to complete the operation (if a program hangs, this could be the problem). code fetching from external memories needs the clock for the ale/ psen timing (e.g. ljmp 5000h needs this clock for completion). when the enb bit has been set by software, the clock will be available internally after the start-up time of this oscillator. the start-up time is 2 to 3 periods of the 76.8 khz reference frequency.
1998 nov 02 35 philips semiconductors product speci?cation pager baseband controller pca5010 6.12.2 6 mh z o scillator c ontrol r egister (os6con) the os6con special function register is used to control the operation of the on-chip 6 mhz oscillator. the 6 mhz oscillator can be controlled as follows: it can be enabled or disabled. disabling this oscillator when the dc/dc converter is in standby mode and no port i/o nor i 2 c-bus activity is required saves current. the frequency of the oscillator can be adjusted by setting the sfx bits accordingly the actual frequency of this oscillator can be measured by writing the mfr bit to logic 1. table 24 6 mhz oscillator control register (os6con, sfr address d3h) table 25 description of the os6con bits 6.12.3 6 mh z o scillator m easured f requency r egister (os6m0) the actual frequency of the 6 mhz on-chip oscillator can be calculated from the value in the os6m0 special function register, after a measure frequency operation (mfr). table 26 6 mhz oscillator measured frequency register (os6m0, sfr address d4h) the value stored in this sfr is the counted number of 6 mhz cycles during one 76.8 khz period. the frequency of the 6 mhz oscillator is therefore f = mf 76800 hz with a resolution of 76800 hz. 76543210 enb - sf4 sf3 sf2 sf1 sf0 mfr bit symbol function os6con.7 enb enable oscillator . if enb = 1 then the function is enabled. the enable bit is only cleared when the processor writes the bit to logic 0, or if the dc/dc converter is put into off state and a reset is generated during the following power-up sequence. os6con.6 - unused os6con.5 sf4 set frequency . this 5-bit value adjusts the current of the ring oscillator and thus the frequency. writing a small value decreases the frequency. the nominal frequency of 6 mhz is assigned to code ( sf4, sf3, sf2, sf1, sf0) = 00000. the resolution of the frequency adjustment is 200 khz per step, the range is approximately 3 to 9 mhz. in order to start with the nominal frequency the msb is inverted in this sfr. os6con.4 sf3 os6con.3 sf2 os6con.2 sf1 os6con.1 sf0 os6con.0 mfr measure frequency . if a positive pulse is issued on this sfr-bit a frequency measurement cycle is executed. the duration of this cycle is one period of 76.8 khz. the count of 6 mhz periods during the measurement cycle is reported back in os6m0. the bit must be reset by software. 76543210 mf7 mf6 mf5 mf4 mf3 mf2 mf1 mf0
1998 nov 02 36 philips semiconductors product speci?cation pager baseband controller pca5010 6.12.4 e nabling of the 6mh z oscillator fig.19 relationship between 6 mhz oscillator, dc/dc converter and microcontroller. handbook, full pagewidth mgr120 microcontroller dc/dc converter os6con, enb i 2 c-bus serial interface px s0con, s0buf port i/o external access & 3 1 6 mhz oscillator enb f6m enb 6.13 real-time clock 6.13.1 f unction the real-time clock consists of an 8-bit counter that is active at all times. to save power it is operated directly on v bat . it counts up on every 4 hz clock pulse (corrected clock). the rtc can be read from and written to by the processor. when it reaches 239, the signal minute is activated. this signal resets the counter to 0 (at the next clock pulse), and generates an min-interrupt for the processor. the microcontroller sees the minute interrupt as if it was an x9 interrupt. it can be enabled and disabled and must be cleared as an x9 interrupt (clr iq9). if the dc/dc converter is not active when this happens, the dc/dc converter is started first and a power-up/restart sequence of the microcontroller follows. the min bit remains set during this procedure. 6.13.2 r eal -t ime c lock c ontrol r egister (rtcon) the rtccon special function register is used to control the operation of the on-chip real-time clock function.
1998 nov 02 37 philips semiconductors product speci?cation pager baseband controller pca5010 table 27 rtc control register (rtccon, sfr address cdh) table 28 description of the rtcon bits 6.13.3 r eal -t ime c lock d ata r egister (rtc0) table 29 rtc data register (rtc0, sfr address ceh) the value stored in this sfr is the actual 4 hz count since the last minute interrupt. the contents of this counter can be read from and written to by software. the contents of this counter are only initialized when resetin is activated. during an off sequence, the rtc continues its operation. the value of the rtc data register is only updated while the stb flag in the dccon0 sfr is high, i.e. the dc/dc converter is able to sustain the v dd supply voltage. if the stb flag is logic 0 the real-time clock continues its operation, the minute interrupt occurs regularly, but the sfr is not updated. 76543210 min ---- w/ r load set bit symbol function rtcon.7 min min is activated when the counter reaches 239 . min is used to generate the interrupt request signal minute. in order to complete the interrupt cycle and reset the interrupt source, the processor has to clear min. this must be done in a 2 step operation writing min and then applying a positive edge to set. rtcon.6 - unused rtcon.5 - unused rtcon.4 - unused rtcon.3 - unused rtcon.2 w/ r before the rtc time can be set by software, the updating of the sfr by the rtc must be disabled. this is done by writing the w/ r bit to logic 1. the w/ r bit is cleared by hardware after the next 4 hz clock, when the rtc has been loaded with its next value. rtcon.1 load load rtc with contents of rtc0 . load is sampled with the positive edge of the set ?ag set. if load is not high during a set operation, only the min ?ag is (re)set by the command. rtcon.0 set latch signal for the real-time clock . with the pulse on set the content of min is copied into the real min latch. this is necessary because the rtc has to be active at all times independant of the microcontroller. 76543210 qsecs7 qsecs6 qsecs5 qsecs4 qsecs3 qsecs2 qsecs1 qsecs0
1998 nov 02 38 philips semiconductors product speci?cation pager baseband controller pca5010 6.13.4 e xample sequence for programming the rtc: sequence to set another value into the rtc: mov rtcon, #06h; set load, w/ r bits mov rtc0, #(new value); load new rtc value into sfr mov rtcon, #07h; now set the data valid flag (set) in the sfr. sequence to clear an interrupt of the rtc: clr iq9; interrupt request flag is iq9 mov rtcon, #00h; clear also min flag in the sfr mov rtcon, #01h; now set the data valid flag (set) in the sfr. 6.13.5 t iming the interface between 2 and 1 v regions is implemented similar to the clock correction block. the sequence for writing values is identical (see fig.15). fig.20 operation of rtc to microcontroller interface. handbook, full pagewidth mgr121 load (rtcon) set (rtcon) internal set flag internal store internal write rtc value w/r (rtcon) data (rtc0) 4 hz mov rtc0 #m mov rtcon #... data must be valid until here cleared by hardware update by hardware im i + 1 ii + 1 update by hardware m + 1 mm + 1
1998 nov 02 39 philips semiconductors product speci?cation pager baseband controller pca5010 6.14 wake-up counter 6.14.1 f unction the wake-up counter is intended to be used as protocol timer. it can be programmed to wake-up the processor when the protocol needs an action. amongst others this may be: switching on the dc/dc converter at time 0 enabling the receiver at time 1 enabling the demodulator and clock recovery function at time 2 before relevant data is expected. the time to wake-up is defined as a 16-bit value containing the number of 9600 hz ticks. the maximum time interval that can be spawn with one cycle then equals 6.8 s. the wake-up counter and its reload latch are supplied by v bat and work independent of the 2 v supply. a reset to the microcontroller does not clear the wake-up counter control flags or the reload latch, but clears the reload register (see fig.21). the counter is implemented as a 16-bit ripple down counter. it can be loaded from the wake-up reload latch by a signal from the processor. when the counter is loaded it automatically starts if the run signal is active. when the counter reaches zero the wake-up signal becomes active and may generate an interrupt. the wake-up signal automatically reloads the counter (modulo n counter). the counter is stopped when the run signal is written to logic 0. auto reloading of the counter is also possible, when the dc/dc converter is not operating (i.e. v dd is below 1.8 v). the contents of the wake-up counter cannot be read by the processor. reading wuc0 and wuc1 reflects the contents of the 16-bit wake-up register (set by the microcontroller). the interface between 2 and 1 v regions is implemented similar to the clock correction block. the sequence for writing values is identical (see fig.16). fig.21 block diagram of wake-up counter. handbook, full pagewidth mgr122 qd q r d 1 store 9600 hz internal set flag sfr to microcontroller reset with each off cycle set cpl run load wup test z1 z0 wu0 to wu15 wu reload latch (16-bit) reload data wu counter (16-bit) & interrupt 3 1 3 1 reload v dd supply wake-up dc/dc converter v bat supply carry reset only on resetin
1998 nov 02 40 philips semiconductors product speci?cation pager baseband controller pca5010 6.14.2 w ake -u p c ounter c ontrol r egister (wucon) the wucon special function register is used to control the operation of the wake-up counter by software. table 30 wake-up counter control register (wucon, sfr address 94h) table 31 description of the wucon bits 6.14.3 w ake -u p d ata r egisters (wuc0 and wuc1) the wuc0 and wuc1 special function registers are used to define the interval to the next wake-up interrupt. table 32 low wake-up register (wuc0, sfr address 95h) table 33 high wake-up register (wuc1, sfr address 96h) 76543210 run wup test cpl z1 z0 load set bit symbol function wucon.7 run control signal from the processor. wucon.6 wup latched wake-up signal . the bit is set by hardware (or software) and generates a wake-up interrupt if enabled and the dc/dc converter stb-bit is set. the bit needs to be cleared by software (sfr and 1 v bits). a set sequence is required to clear the ?ag on the 1 v side. attention: reading the bit reads the contents of the real wake-up ?ag on the 1 v side (read/modify/write commands will fail on this bit). wucon.5 test test control signal . (uses 76.8 khz as clock input for high and low counter). wucon.4 cpl set operation completed . bit set by hardware when the last operation is completed and the sfrs are again ready to accept new settings. the bit generates a wake-up interrupt if enabled. the bit needs to be cleared by software. wucon.3 z1 2 bits that are only reset by a primary resetin. the bits can be written to and read from by the software. the bits are not cleared when the dc/dc converter is switched off. same procedure for setting the bits as wu0 to wu15 (reading these bits returns the real ?ags on the 1 v side; read/modify/write commands will fail on this bit). wucon.2 z0 wucon.1 load load wake-up counter with contents of reload latch (see fig.21). is sampled on the positive edge of set. wucon.0 set clock signal for writing to run or wake-up sfr (on 1 v level). 76543210 wu7 wu6 wu5 wu4 wu3 wu2 wu1 wu0 76543210 wu15 wu14 wu13 wu12 wu11 wu10 wu9 wu8
1998 nov 02 41 philips semiconductors product speci?cation pager baseband controller pca5010 wu0 to wu15 is a 16-bit register that is loaded by the processor. the contents of this register will be loaded into a 16-bit reload latch with a positive pulse on set and into the 16-bit ripple down counter with a positive pulse on load. the value stored in the wake-up counter cannot be read by software. the contents of this counter are only initialized when resetin is activated. during an off sequence the wake-up counter continues its operation. the wake-up-interrupt can only occur while the stb flag in the dccon0 sfr is high, i.e. the dc/dc converter is able to sustain the v dd supply voltage. if the stb flag is logic 0 the wake-up counter continues its operation, the wake-up flag is set when expired (and can still be checked by software), but an interrupt is not generated. 6.14.4 e xample sequence for controlling the wake - up counter sequence to set another reload value: mov wuc1, #(high value) mov wuc0, #(low value) mov wucon, #82h; set run and load bit mov wucon, #83h; activate set flag mov pcon, #01h; >>> idle, wait for cpl interrupt. 6.14.5 t iming fig.22 operation of wake-up counter to microcontroller interface. handbook, full pagewidth mgr123 set bit in sfr internal set flag internal store internal data counter value load data in sfr 9600 hz cpl bit in wucon (generates interrupt if enabled) transfer to 1 v registers completed, data may change again cleared by software set by hardware m m ii - 1 mm - 1
1998 nov 02 42 philips semiconductors product speci?cation pager baseband controller pca5010 6.15 tone generator 6.15.1 f unction the tone generator is implemented by a programmable divider from 76.8 khz. an 8-bit value is used to define the cycle of a modulo n counter. the output of the modulo n counter is divided-by-2 to produce a symmetrical output signal. the counter is running when enabled. the output frequency at the pin at is defined as: if tfreq 3 1. if tfreq = 0 then f at = 76.8 khz. a secondary clock signal can be used as clock input to the modulo n counter. this input is required to generate the accurate resonance frequency of certain acoustic alerters (e.g. 512, 687, 1024, 1365, 2048, 2730 or 4096). the tone volume can be controlled by setting the frequency on or off alerter resonance. 6.15.2 i nterfaces sfr addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tgcon (92h) enb clk2 ------ tg0 (93h) tfreq7 tfreq6 tfreq5 tfreq4 tfreq3 tfreq2 tfreq1 tfreq0 fig.23 wake-up interrupt sequence. handbook, full pagewidth mgr124 internal set flag counter value set bit in sfr load 9600 hz wup flag on 1 v side generates dc/dc wake-up if required wup in wucon sfr (generates interrupt if enabled) cpl in wucon sfr (generates interrupt if enabled) cleared by software cleared by software set by hardware set by hardware wup remains high if not cleared set by hardware mm - 1 0 set to transfer modified wup to 1 v side only wucon data to be transferred, no reload for wuc0, wuc1 sfr and 1 v wup are different f at 76.8 khz tfreq ----------------------- =
1998 nov 02 43 philips semiconductors product speci?cation pager baseband controller pca5010 sfr: tfreq0 to tfreq7: 8-bit register containing the divisor of the tone. loaded by the processor. enb: enable frequency generator. control signal from processor. clk2: use secondary clock input for tone generation. if set a 32768 hz clock signal is generated from the primary 76800 hz clock signal and used as a timing reference for the tone generator. inputs: 76.8 khz: input to the tone counter. outputs: at output for alerter. is logic 0 when disabled: 6.15.3 g eneration of the 32768 h z reference the 32768 hz reference is generated from 76800 hz according to the following algorithm: forever do begin for 10 times do { from 7 clocks on 76.8 khz generate 3 pulses on 32 khz } from 5 clocks on 76.8 khz generate 2 pulses on 32 khz end f at 76.8 khz tfreq ----------------------- = 6.16 watchdog timer 6.16.1 f unction the watchdog timer consists of an 8-bit down counter. the binary number defined with wd3 to wd0 defines the expiration time of the watchdog timer between 1 to 16 s. once enabled this counter is running continuously. once expired the timer produces firstly an interrupt and finally a reset. the software must reload the watchdog in regular intervals to avoid expiration. a positive edge on the ld sfr bit (re)loads the counter with the value of wd3 to wd0, sets the low bits to logic 1 and activates this counter if it is not yet running. however, to prepare the (re)loading a positive edge must be applied to the cond bit in wdcon. in this way at least two locations in software must be passed before the counter can be reloaded. after reset the counter is not running. only after the first ld it is clocked continuously by a clock pulse of 16 hz until the dc/dc converter is switched off or an external reset is applied. if the next ld signal is not given within the defined expiry interval an overflow occurs and the processor will be reset (signal wdr). 1 clock cycle before the reset is applied an wdi interrupt is issued. this gives the opportunity to avoid the reset if required. the maximum watchdog expiry time is thus 254 16 hz ticks to the wd interrupt and 255 16 hz ticks to the reset. if the dc/dc converter is in the off mode, the watchdog timer is suspended. 6.16.2 w atch d og t imer c ontrol r egister (wdcon) the wdcon special function register is used to control the operation of the on-chip watchdog timer. table 34 watchdog control register (wdcon, sfr address a5h) table 35 description of the wdcon bits 76543210 cond wd3 wd2 wd1 wd0 -- ld bit symbol function wdcon.7 cond load condition . control signal from processor. wdcon.6 wd3 wd0 to wd3 is the preset value for the high nibble of the watchdog timer. the value is the number of seconds to expiry of the watchdog. wdcon.5 wd2 wdcon.4 wd1 wdcon.3 wd0
1998 nov 02 44 philips semiconductors product speci?cation pager baseband controller pca5010 wdcon.2 - unused wdcon.1 - unused wdcon.0 ld load watchdog timer with wd0 to wd3 . control signal from processor. bit symbol function 6.16.3 s ample sequence to reload the watchdog the sequence to reload the watchdog with 1 s is: mov wdcon, #80h; prepare condition mov wdcon, #01h; reload the timer. 6.17 2 or 4-fsk demodulator, ?lter and clock recovery circuit 6.17.1 f unction the aim of the blocks demodulator and clock recovery circuitry is to take the signal from the receiver, to format it into symbols and to transfer it to the processor. the two blocks use the 76.8 khz clock. the demodulator decodes the incoming signal and generates a sequence of nrz data. this data is fed to the clock recovery block which regenerates the synchronization clock. this clock is used to sample and to shift the symbols into the register dmd3. each block is enabled separately. to save power, the functions should be disabled whenever not needed. 6.17.1.1 demodulator and ?lter the demodulator can operate both with 2-level or 4-level fsk input signals (selectable by means of bit lev). for both types of input signals the so called demodulator, filter and direct modes are allowed. the operation mode is selected on the basis of m bit and bf bit. in the demodulator mode (m = 0 and bf = x) the i and q signals are decoded according to table 36. operating in this mode, an offset compensation can be performed and the calculated offset value is stored into register dmd1, in the field avg. the offset value can be used by the processor to adjust the analog afc output voltage. the offset coding is given in table 37. the performance of the demodulator for the different baud rates in 2l mode is shown in fig.24 and for 4l mode in fig.25. the graphs show the bit error rate (ber) as a function of eb/no (ratio of signal energy per bit to average noise power per unit bandwidth). both the filter and direct modes are intended for application with an external demodulator. in this case nrz data is fed to the i and q pins. in the 4-fsk case, the msb is at pin i and the lsb is at pin q. in the 2-fsk situation, only the i pin is used while pin q must be connected to v ss . in these two modes, the offset calculation and compensation cannot be performed. in the filter mode (m = 1 and bf = 0), the data is filtered and then sent to the clock recovery. the filter characteristics of the implemented filter are shown in fig.26. in the direct mode (m = 1 and bf = 1), no function of the demodulator is performed. consequently there is no filtering on the data which is sent directly to the clock recovery. table 36 modulation coding table 37 offset coding (2s complement) frequency (hz) 2-fsk 4-fsk d1 d0 d1 d0 +4800 1 x 1 0 +1600 1 x 1 1 - 1600 0 x 0 1 - 4800 0 x 0 0 offset (hz) code (avg6 to avg0) - 9450 0111111 - 9300 0111110 ... ... - 300 0000010 - 150 0000001 0 0000000 150 1111111 300 1111110 ... ... 9300 1000001 9450 1000000
1998 nov 02 45 philips semiconductors product speci?cation pager baseband controller pca5010 fig.24 demodulator performance in 2l mode. handbook, full pagewidth 10 2 10 - 2 10 - 1 1 10 17 3 mgr339 913 715 eb/no 511 ber (%) (2) (3) (4) (5) (1) (1) 2 level 1200. (2) 2 level 1600. (3) 2 level 3125. (4) 2 level 2400. (5) 2 level 3200. handbook, full pagewidth 10 2 10 - 2 10 - 1 1 10 17 3 mgr340 913 715 eb/no 511 ber (%) (2) (3) (4) (5) (1) (1) 4 level 1200. (2) 4 level 1600. (3) 4 level 3125. (4) 4 level 2400. (5) 4 level 3200. fig.25 demodulator performance in 4l mode.
1998 nov 02 46 philips semiconductors product speci?cation pager baseband controller pca5010 fig.26 filter characteristics in direct filter mode. handbook, full pagewidth 10 - 40 10 2 10 3 10 4 mgr341 - 30 - 20 - 10 0 amplitude (db) f (hz) 1600 1200 2400 3125 3200 6.17.1.2 clock recovery the clock recovery regenerates the synchronization clock using the edges of the incoming nrz data. when the nrz data have no edges for a long time, the synchronization is maintained by means of the correction information from the clock correction block. while the clock recovery is disabled, the momentary phase of the recovered clock is frozen. if the clock recovery is enabled at the same relative position within one bit, where it was disabled, then the recovered clock phase will be correct immediately. the recovered clock is used to sample and shift to left into an internal register one bit each symbol period in 2-fsk and two bits in 4-fsk. the symbol period is determined by bits bd2 to bd0. on the basis of bd bits the demodulator filter length is also set. in the clock recovery, a pulse (symclk) is generated each n-bits, where n is defined by means of bits b2 to b0. this pulse is used to update the register dmd3. moreover, it can be used as interrupt to the processor through the irq1.3 (symbol interrupt). the interrupt informs the controller that n bits are available in the register dmd3. the worst case time required to synchronize to incoming data, when completely out of phase, is plotted for the different baud rates in the following figure (see fig.27).
1998 nov 02 47 philips semiconductors product speci?cation pager baseband controller pca5010 6.17.1.3 baud rate selection no bits are lost when switching between single and double baud rates as e.g. required for high speed protocol synchronization. figure 27 shows how the pca5010 reacts in this situation. fig.27 transient phase error due to an input signal phase step of 180 degrees for the different baud rates. handbook, full pagewidth 0 204060 180 0 140 160 mgr342 (2) (4) (3) (5) (1) 10 30 50 100 60 20 120 80 40 phase error number of symbols (time = nr. symbol/baud) (1) 2 level 1200. (2) 2 level 1600. (3) 2 level 3125. (4) 2 level 2400. (5) 2 level 3200. fig.28 switching between single and double baud rates (e.g. advanced high speed paging protocol synchronization). handbook, full pagewidth mgr343 demodulated filtered data recovered symbol clock (symbol interrupt) 2t 2t t interval allowed for the software to change the baud rate < 1.5t - d< 1t - d ( d = 1/76800 s) 3200 bits/s [t = 1/3200 (s)] 1600 bits/s 1600 bits/s
1998 nov 02 48 philips semiconductors product speci?cation pager baseband controller pca5010 6.17.2 d emodulator c ontrol r egister (dmd0) the demodulator control register dmd0 contains the control bits for enabling the demodulator function and setting its mode and data rate. table 38 demodulator control register (dmd0, sfr address ech) table 39 description of the dmd0 bits table 40 baud rate for bits bd2, bd1 and bd0 6.17.3 d emodulator averaging r egister (dmd1) the demodulator averaging register dmd1 contains the control bit for enabling the averaging function, used for the offset compensation during demodulation and the coded average (offset) value. table 41 demodulator averaging register (dmd1, sfr address edh) 76543210 enb m - res lev bd2 bd1 bd0 bit symbol function dmd0.7 enb enable demodulator function dmd0.6 m mode selection: logic 0 = i/q from zero-if receiver, logi c 1 = nrz data dmd0.5 - not used dmd0.4 res reserved for future implementation dmd0.3 lev if set to logic 0 2-fsk demodulation, if set to logic 1 4-fsk demodulation dmd0.2 bd2 baud rate setting; see table 40 dmd0.1 bd1 dmd0.0 bd0 bits baud rate bd2 bd1 bd0 0 0 0 1200 symbols/s 0 0 1 2400 symbols/s 0 1 0 1600 symbols/s 0 1 1 3200 symbols/s 1 0 0 unde?ned 1 0 1 unde?ned 1 1 0 unde?ned 1 1 1 3125 symbols/s 76543210 ena avg6 avg5 avg4 avg3 avg2 avg1 avg0
1998 nov 02 49 philips semiconductors product speci?cation pager baseband controller pca5010 table 42 description of the dmd1 bits 6.17.4 c lock r ecovery c ontrol r egister (dmd2) the clock recovery control register dmd2 contains the control bits for enabling the clock recovery function and setting its mode. whenever the clock recovery function is enabled (dmd2.7 = 1) the positive edge of the synchronized symclk signal will force a symclk interrupt through the irq1.3 request flag after [b2, b1 and b0] received bits (see table 50). table 43 clock recovery control register (dmd2, sfr address eeh) table 44 description of the dmd2 bits 6.17.5 d emodulator d ata r egister (dmd3) the demodulator data register dmd3 contains the (demodulated) recovered received symbols. table 45 demodulator data register (dmd3, sfr address efh) bit symbol function dmd1.7 ena enable averaging function/offset calculation dmd1.6 avg6 7-bit value indicating the offset value of the demodulator. this is an indication of the lo offset frequency and will be used to determine the afc output voltage. for coding see table 37. dmd1.5 avg5 dmd1.4 avg4 dmd1.3 avg3 dmd1.2 avg2 dmd1.1 avg1 dmd1.0 avg0 76543210 enc - bf - test b2 b1 b0 bit symbol function dmd2.7 enc enable clock recovery function dmd2.6 - not used dmd2.5 bf bypass demodulator ?lter dmd2.4 - not used dmd2.3 test reserved, should always be logic 0 dmd2.2 b2 select number of bits per interrupt: dmd2.1 b1 if lev = 0 then 000 = 1-bit, 001 = 2-bit to 111 = 8-bit dmd2.0 b0 if lev = 1 then 00x = 2-bit, 01x = 4-bit, 10x = 6-bit, 11x = 8-bit 76543210 d7 d6 d5 d4 d3 d2 d1 d0
1998 nov 02 50 philips semiconductors product speci?cation pager baseband controller pca5010 table 46 description of dmd3 bits 6.18 afc-dac 6.18.1 f unction the afc digital-to-analog converter provides an analog signal to the receiver to reduce its frequency offset. the analog signal is available at pin 18 (afcout). for low noise sensitivity the dac output is buffered and can drive a load impedance of 10 k w (max.). the output swing is from rail-to-rail v dd . when the enable signal enb bit symbol function dmd3.7 d7 recovered symbols. the number of relevant bits is set with dmd2[2 to 0]. dmd3.6 d6 dmd3.5 d5 dmd3.4 d4 dmd3.3 d3 dmd3.2 d2 dmd3.1 d1 dmd3.0 d0 is at logic 1 a linear binary conversion is performed according to table 47. below 0.2 v the linearity of the output voltage is not ideal. when enb is logic 0 the afcout pin is tied to v ss and all currents are switched off. table 47 coding of afc-dac 6.18.2 afc-dac c ontrol /d ata r egister (afcon) the afc-dac control/data register afcon contains the control bit for enabling the afc-dac and the data bits for setting the output voltage. code output voltage 000000 0 000001 1 1 64 v dd ... ... nn 1 64 v dd ... ... 111111 63 1 64 v dd table 48 afc-dac control/data register (afcon, sfr address 9eh) table 49 description of the afcon bits 76543210 enb - afc5 afc4 afc3 afc2 afc1 afc0 bit symbol function afcon.7 enb enable dac output. afcon.6 - not used. afcon.5 afc5 6-bit value for dac output according to table 47. afcon.4 afc4 afcon.3 afc3 afcon.2 afc2 afcon.1 afc1 afcon.0 afc0
1998 nov 02 51 philips semiconductors product speci?cation pager baseband controller pca5010 6.19 interrupt system external events and the real-time-driven on-chip peripherals require service by the cpu asynchronously to the execution of any particular section of code. to tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. the interrupt system is shown in fig.34. the pca5010 acknowledges interrupt requests from fifteen sources as follows: int0 to int4 and int6 timer 0 and timer 1 wake-up counter i 2 c-bus serial i/o uart transmitter and receiver demodulator dc/dc converter watchdog timer real-time clock (minute). each interrupt vectors to a separate location in program memory for its service routine. each source can be individually enabled or disabled by its corresponding bit in the interrupt enable registers (ien0 and ien1). the priority level is selected via the interrupt priority registers (ip0 and ip1). all enabled sources can be globally disabled or enabled. 6.19.1 o verview the interrupt controller implemented in the pca5010 has 15 interrupt sources, of which some are level sensitive and some are edge sensitive. the interrupt controller samples all active sources during one instruction cycle. evaluation of the interrupts is then performed. a priority decoder decides which interrupt is serviced. each interrupt has its own vector pointing to an 8 bytes long program segment. a low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt i.e. only two interrupt levels are possible. between the reti instruction (return from interrupt) and the lcall to a next interrupt vector at least one instruction of the lower program level is executed (see fig.29). an interrupt is performed with a long subroutine call (lcall) to vector address, which is determined by the respective interrupt. during lcall the pc is pushed onto the stack. returning from interrupt with reti, the pc is popped from the stack. fig.29 interrupt hierarchy. handbook, full pagewidth mgr125 interrupt level 2x interrupt level 1 program level 0 reti level 21 reti level 20 reti one instruction ip = 1 ip = 1 ip = 0
1998 nov 02 52 philips semiconductors product speci?cation pager baseband controller pca5010 6.19.2 i nterrupt process sample the interrupt lines: the interrupt lines are latched at the beginning of each instruction cycle. analyse the requests: the sampled interrupt lines will be analysed with respect to the relevant interrupt enable register (iex) and interrupt priority register (ipx). the process will deliver the vector of the highest interrupt request and the priority information. depending on the interrupt level and the priority of the interrupt in progress, an interrupt request to the core is performed. the vector address will be passed to the core process. interrupt request to core: level 0: the interrupt request to the core is performed, when at least one instruction is performed since the reti from level 1. level 1: the interrupt request is performed, when at least one instruction is performed since the reti from level 21 and the request has high priority. level 20: no request is performed. level 21: no request is performed. emulation: in break mode no interrupt request is performed. update the interrupt level: level 0: in the event of a high priority interrupt the new level will be level 20. if it is a low priority interrupt, the new level will be level 1. level 1: in the event of a high priority interrupt, the new level will be level 21. a low priority interrupt is not performed, the level is unchanged. on reti the new level will be level 0. level 20: on reti, the new level is level 0. level 21: on reti, the new level is level 1. level 1: on reti, the new level is level 0. level 0: the new level is level 0. clearing the flags: during the forced lcall the interrupt flag of the relevant interrupt is cleared by hardware, if applicable, otherwise by software. emulation: during emulation the interrupts may be disabled. this is performed during break mode. with intd asserted, all the interrupts are disabled. idle and power-down: when idle (pcon.0) or power-down (pcon.1) is set, the interrupt controller waits for the according wui signal. because the interrupt controller is waiting for wui, all activity in the circuit will be stopped, thus no handshake can be completed. the wui signal for idle is the or of all the interrupt request bits and the reset. for power-down the wui signal is built only with the port 1 interrupt request flags and the reset. 6.19.3 i nterrupt controller related sfr s the implementation of the interrupt controller related sfrs for enabling and disabling interrupts is identical to a standard 80c51, but the interrupt sources have been changed according to table 50.
1998 nov 02 53 philips semiconductors product speci?cation pager baseband controller pca5010 table 50 interrupt controller related sfrs: ien0 (a8h), ien1 (e8h), ip0 (b8h), ip1 (f8h), irq1 (c0h), tcon (88h), wucon (94h) and rtcon (cdh) bits conv. name source notes ien0 address a8h: interrupt enable for x0, x1, t0, t1, t2, s0, s1 and global interrupt enable 0 ex0 p3.2 enables or disables external0 interrupt. if ex0 = 0, the external interrupt 0 is disabled. 1 et0 timer0 enables or disables the timer 0 over?ow interrupt. if et0 = 0, the timer 0 interrupt is disabled. 2 ex1 p3.3 enables or disables the external1 interrupt. if ex1 = 0, external interrupt 1 is disabled. 3 et1 timer1 enables or disables timer 1 over?ow interrupt. if et1 = 0, the timer 1 interrupt is disabled. 4 es0 uart enables or disables the uart interrupt. if es0 = 0, the uart interrupt is disabled. 5 es1 i 2 c enables or disables the i 2 c-bus interrupt. if es1 = 0, the i 2 c-bus interrupt is disabled. 6 et2 wake-up enables or disables the wake-up interrupt. if et2 = 0, the wake-up interrupt is disabled. 7 ea / disables all interrupts. if ea = 0, no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ien1 address e8h: interrupt enable for x2 to x9 0 ex2 p1.0 enables or disables interrupts on p1.0. if ex2 = 0, the corresponding interrupt is disabled. 1 ex3 p1.1 enables or disables interrupts on p1.1. if ex3 = 0, the corresponding interrupt is disabled. 2 ex4 p1.2 enables or disables interrupts on p1.2. if ex4 = 0, the corresponding interrupt is disabled. 3 ex5 symbol enables or disables the symbol interrupt. if ex5 = 0, the symbol interrupt is disabled. 4 ex6 p1.4 enables or disables interrupts on p1.4. if ex6 = 0, the corresponding interrupt is disabled. 5 ex7 dc/dc enables or disables the dc/dc converter interrupt. if ex7 = 0, the dc/dc converter interrupt is disabled. 6 ex8 wdi enables or disables interrupts on the watchdog. if ex8 = 0, the wdint interrupt is disabled. 7 ex9 min enables or disables real-time clock interrupt. if ex9 = 0, the minute interrupt is disabled. ip0 address b8h: interrupt priority for x0, x1, t0, t1, s0 and s1 0 px0 p3.2 de?nes the external0 interrupt 0 priority level. px0 = 1 programs it to the higher priority level. 1 pt0 timer0 enables or disables the timer 0 interrupt priority level. pt0 = 1 programs it to the higher priority level. 2 px1 p3.3 de?nes the external1 interrupt priority level. px1 = 1 programs it to the higher priority level. 3 pt1 timer1 de?nes the timer 1 interrupt priority level. pt1 = 1 programs it to the higher priority level.
1998 nov 02 54 philips semiconductors product speci?cation pager baseband controller pca5010 4 ps0 uart de?nes the uart interrupt priority level. ps0 = 1 programs it to the higher priority level. 5 ps1 i 2 c de?nes the i 2 c-bus interrupt priority level. ps1 = 1 programs it to the higher priority level. 6 pt2 wake-up de?nes the wake-up interrupt priority level. pt2 = 1 programs it to the higher priority level. 7 - / unused. ip1 address f8h: interrupt priority for x2 to x9 0 px2 p1.0 de?nes the external2 interrupt priority level 1. px2 = 1 programs it to the higher priority level. 1 px3 p1.1 de?nes the external3 interrupt priority level 1. px3 = 1 programs it to the higher priority level. 2 px4 p1.2 de?nes the external4 interrupt priority level 1. px4 = 1 programs it to the higher priority level. 3 px5 symbol de?nes the symbol interrupt priority level 1. px5 = 1 programs it to the higher priority level. 4 px6 p1.4 de?nes the external6 interrupt priority level 1. px6 = 1 programs it to the higher priority level. 5 px7 dc/dc de?nes the dc/dc converter interrupt priority level 1. px7 = 1 programs it to the higher priority level. 6 px8 wdi de?nes the watchdog interrupt priority level 1. px8 = 1 programs it to the higher priority level. 7 px9 min de?nes the real-time clock interrupt priority level 1. px9 = 1 programs it to the higher priority level. tcon address 88h: timer/counter mode control register 0 it0 p3.2 external0 interrupt type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt. 1 ie0 p3.2 external0 interrupt ?ag. set by hardware when external interrupt detected. cleared by hardware. 2 it1 p3.3 external1 interrupt type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt. 3 ie1 p3.3 external1 interrupt ?ag. set by hardware when external interrupt detected. cleared by hardware. 4 tr0 timer0 timer 0 run control bit. set/cleared by software to turn timer on/off. 5 tf0 timer0 timer 0 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hard or software. 6 tr1 timer1 timer 1 run control bit. set/cleared by software to turn timer on/off. 7 tf1 timer1 timer 1 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hard or software. irq1 address c0h: interrupt request register for x2 to x9 0 iq2 p1.0 interrupt request ?ag from p1.0. 1 iq3 p1.1 interrupt request ?ag from p1.1. 2 iq4 p1.2 interrupt request ?ag from p1.2. bits conv. name source notes
1998 nov 02 55 philips semiconductors product speci?cation pager baseband controller pca5010 notes 1. ien0 and ien1: these are two 8-bit registers that control the enabling of the 15 interrupt sources individually as well as a global enable/disable for all of the sources. 2. ip0 and ip1: these are two 8-bit registers that set priority for each interrupt source. ip0 actually contains only 7 bits as ip.7 is not implemented. this bit will always read as logic 0. 3 iq5 symbol interrupt request ?ag from clock recovery circuit. set by hardware or software. cleared by software. 4 iq6 p1.4 interrupt request ?ag from p1.4. 5 iq7 dc/dc interrupt request ?ag from dc/dc-converter. set by hardware or software. cleared by software. 6 iq8 wdi interrupt request ?ag from watchdog timer. set by hardware or software. cleared by software. 7 iq9 min interrupt request ?ag from real-time clock interrupt. set by hardware or software. cleared by software. wucon address 94h: wake-up counter control register 0 set - latch signal to copy content of wuc to peripheral register. 1 load - parallel load signal for wake-up counter. 2z0 - 3z1 - 4 cpl - complete interrupt ?ag from wake-up counter timer. set by hardware or software. cleared by software. 5 unused - 6 wup - wup interrupt ?ag from wake-up counter timer. set by hardware or software. cleared by software. 7 run - run bit for wake-up counter. rtcon address cdh: real-time clock control register 0 set - latch signal to copy content of wuc to peripheral register. 1 load - load rtc0 value from sfr to rtc. 2w/ r - disable write back to sfr. 3 to 6 unused - 7 min - interrupt request ?ag from rtc. set by hardware or software. cleared by software. bits conv. name source notes
1998 nov 02 56 philips semiconductors product speci?cation pager baseband controller pca5010 6.19.4 p ort 3 interrupts : p3.2 and p3.3 int0 and int1 are level or edge sensitive. the programming is performed with tcon. since p3.2 and p3.3 are configured as push-pull outputs, these interrupts can only be triggered by output commands to these ports and not by external events. tcon.0 (it0): interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt (see fig.30). tcon.1 (ie0): interrupt 0 flag. set by hardware when an external interrupt is detected. cleared by hardware when the service routine is called. tcon.2 (it1): interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt. tcon.3 (ie1): interrupt 0 flag. set by hardware when an external interrupt is detected. cleared by hardware when the service routine is called. 6.19.5 w ake - up interrupt the wake-up interrupt (t2) is the level sensitive or-function of wup bit or cpl bit in the wucon sfr. the wake-up interrupt is mapped to the t2 vector (see fig.30). these flags are set by hardware and need to be cleared by software. for more information see section 6.14. wucon.6 (wup): wup interrupt flag. attention: writing and reading this sfr bit does not access the same flag. the flag is set by hardware and needs to be cleared by software. wucon.4 (cpl): complete flag. the previous set instruction is completed. the settings of the sfr have been copied to the peripheral block. the flag is set by hardware and needs to be cleared by software. fig.30 external interrupt port 3.2 and port 3.3 (int0 and int1). handbook, full pagewidth pad port 3.2 mgr126 it0 int0 x0 ie0 (interrupt edge flag) 0 1 fig.31 wake-up interrupt. handbook, full pagewidth mgr1127 wake-up counter wup cpl t2 3 1
1998 nov 02 57 philips semiconductors product speci?cation pager baseband controller pca5010 6.19.6 p ort 1 interrupts :p ort 1.0 to p ort 1.4 (int2 to int6) four port 1 lines can be used as external interrupt inputs (see fig.30). when enabled (ien1 sfr), each of these lines may wake-up the device from power-down. using the ix1 register, each of these port lines may be set active to either high or low. irq1 is the interrupt request flag register. each flag, if the interrupt is enabled, will send an interrupt request, but must be cleared by software, i.e. via the interrupt software. the port 1 interrupt request flags can only be set if the corresponding interrupt enable bit is set. 6.19.7 m ore interrupts :s ym c lk , dc/dc, watchdog and minute the decoder blocks generate events that can force an interrupt when enabled (ien0 and ien1 sfr). these interrupts are mapped to the corresponding p1 interrupt request flag register bits (see fig.33). each flag, if the interrupt is enabled, will send an interrupt request and must be cleared by software, i.e. via the interrupt service routine. the irq bits are not set if the corresponding enable is not set. irq1.3: (symbol interrupt): this interrupt request flag, if enabled, is set if the demodulator (clock recovery) has data ready, that should be read by the microcontroller. the event is called symbol clock or symclk, because in one mode of operation one symbol is delivered per interrupt. the flag is set by hardware and needs to be cleared by software. irq1.5: (dc/dc converter interrupt); this interrupt request flag, if enabled, is set if the dc/dc converter is not able to deliver the required current (stb flag cleared). the flag is set by hardware and needs to be cleared by software. irq1.6: (watchdog interrupt); this interrupt request flag, if enabled, is set if the watchdog timer will expire within 1 16 s. the flag is set by hardware and needs to be cleared by software. irq1.7: (minute interrupt). this interrupt request flag, if enabled, is set each minute once by the real-time clock. the flag is set by hardware and needs to be cleared by software. fig.32 interrupt port 1.0. handbook, full pagewidth mgr128 ix1.0 int2 x2 ien1.0 irq1.0 wake-up.0 pad port 1.0 0 1 fig.33 symclk (as example for any of the 4 mentioned interrupts). handbook, full pagewidth mgr129 ien1.3 symclk clock recovery block x5 irq1.3
1998 nov 02 58 philips semiconductors product speci?cation pager baseband controller pca5010 6.19.8 i nterrupt handling figure 34 shows the conventions for interrupt assignments and priorities. arbitration of several simultaneously sampled interrupts can be seen from fig.34. the sampled interrupt with the highest priority will be handled first (assuming that the interrupt priority is default). setting of interrupt request flags for x2 to x9 is masked by the corresponding interrupt enable bit (ien1). fig.34 interrupt assignment and priorities. note: the signal level applied to the ea pin defines whether the interrupt vector code is fetched from external or internal rom. handbook, full pagewidth mgr130 high ip0/1 ien0/1 low 0.0 0.0 tcon.1 ie0 0.5 0.5 s1con.3 si 1.3 1.3 irq1.3 sym 0.1 0.1 tcon.5 tf0 0.6 0.6 wucon.6 wup 1.4 1.4 irq1.4 iq6 0.2 0.2 tcon.3 ie1 1.0 1.0 irq.0 iq2 1.5 1.5 irq1.5 dc 0.3 0.3 tcon.7 tf1 1.1 1.1 irq1.1 iq3 1.6 1.6 irq1.6 wdi 0.4 0.4 s0con.0/1 ti/ri 1.2 1.2 irq1.2 iq4 1.7 1.7 rtcon.7 min 0.7 x0 s1 x5 t0 t2 x6 x1 x2 x7 t1 x3 x8 s0 x4 x9 p3.2 p1.4 p3.3 p1.0 p1.1 p1.2 int0 i 2 c-bus symclk timer 0 wake-up int6 int1 int2 dc/dc timer 1 int3 wdint uart int4 minute hw sw sw hw sw sw hw sw sw hw sw sw sw sw sw 03 name flag port function cleared by vector 2b 53 0b 33 5b 13 3b 63 1b 43 6b 23 4b 73 global enable decreasing priority within same level priority
1998 nov 02 59 philips semiconductors product speci?cation pager baseband controller pca5010 6.20 idle and power-down operation idle and power-down are power saving modes of the microcontroller that can be activated when no cpu activity is required. both modes do not stop the 76.8 khz oscillator nor disable any peripheral function. the following functions remain active during the idle mode: timer 0 and timer 1 wake-up counter watchdog counter real-time clock demodulator and clock recovery uart i 2 c-bus external interrupt. 6.20.1 i dle mode the instruction that sets pcon.0 is the last instruction executed in the normal operating mode before the idle mode is activated. once in the idle mode, the cpu status is preserved together with the stack pointer, program counter, program status word and accumulator. the ram and all other registers maintain their data during idle mode. the status of the external pins during idle mode is shown in table 51. there are two ways to terminate the idle mode: 1. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware thus terminating the idle mode. the interrupt is serviced, and following the reti instruction, the next instruction to be executed will be the one following the instruction that put the device in the idle mode. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when the idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. 2. the second way of terminating the idle mode is with an internal or external hardware reset. reset redefines all sfrs but does not affect the on-chip ram. possible sources of an internal reset are a) watchdog reset if the watchdog had expired b) off/on reset if the dc/dc converter is restarted from off mode (wake-up counter, rtc or p1 pins). 6.20.2 p ower-down mode the instruction that sets pcon.1 is the last instruction executed in the normal operating mode before the power-down mode is activated. once in the power-down mode, the cpu status is preserved together with the stack pointer, program counter, program status word and accumulator. the ram and all other registers maintain their data during power-down mode. the status of the external pins during power-down mode is shown in table 51. there are two ways to terminate the power-down mode: 1. activation of an enabled external interrupt [int2 to int9] will cause pcon.1 to be cleared by hardware thus terminating the power-down mode. the interrupt is serviced, and following the reti instruction, the next instruction to be executed will be the one following the instruction that put the device in the power-down mode. 2. the second way of terminating the power-down mode is with an internal or external hardware reset. reset redefines all sfrs but does not affect the on-chip ram. possible sources of an internal reset are a) watchdog reset if the watchdog had expired b) off/on reset if the dc/dc converter is restarted from off mode (wake-up counter or p1 pins). the power-down mode is not specially useful. it has been implemented for compatibility only. the idle mode has the same power saving capability and allows much more flexible wake-up. 6.20.3 o ff mode the off mode has been designed as the power saving mode of the pca5010. shortly after entering this mode the dc/dc converter is switched off and v dd is reduced to v bat . directly after activating the off mode, the cpu must be set in idle mode. the off mode is entered by: 1. orl dccon0, #80h 2. orl pcon, #01h. the off mode can be exited by one of the following events: rtc minute event wake-up counter event event on any p1 pin resetin active high.
1998 nov 02 60 philips semiconductors product speci?cation pager baseband controller pca5010 each of these events first starts the dc/dc converter to ramp up v dd to 2.2 v. after an initial reset, generated by the dc/dc converter when v dd is again at normal level, all 2 v blocks will restart their operation. the first instruction will be fetched from address 0. the edge sensitive interrupts (minute and wake-up) from the internal sources have been lost during restart and must be polled from their sfrs. events from p1 pins can be served after enabling the interrupts, since they are level sensitive. 6.20.4 s tatus of external pins the status of the external pins during idle and power-down mode is shown in table 51. table 51 status of external pins during normal, idle and power-down modes 6.20.5 p ower c ontrol r egister (pcon) the reduced power modes are activated by software using this special function register. pcon is not bit addressable. table 52 power control register (pcon and sfr address 87h) table 53 power control register (pcon, sfr address 87h) notes 1. this device does not support external xram access. therefore the xre bit is meaningless and should never be written to logic 1. mode memory ale psen port 0 port 1 port 2 port 3 normal internal 0 1 port data port data port data port data idle internal 1 1 port data port data port data port data external 1 1 pull-up high port data address port data power-down internal 0 0 pull-up high port data port data port data external 0 0 pull-up high port data address port data 76543210 smod xre enis - gf1 gf0 pd idl bit symbol function pcon.7 smod control bit to double data rate of uart, when set to logic 1. pcon.6 xre if set to logic 1 enables external xram from address 0 on, if set to logic 0 the ?rst 1024 xram bytes are in internal xram, the higher addresses come from external xram; see note 1. pcon.5 enis enable isync . if bit is set, isync can be monitored at pin ea in internal access mode. the binary value of isync changes each time a new instruction is fetched from memory. this bit must not be set to logic 1 by user program! pcon.4 - reserved. pcon.3 gf1 general purpose ?ag bit . pcon.2 gf0 general purpose ?ag bit . pcon.1 pd power-down bit . setting this bit activates the power-down mode; see note 2. pcon.0 idl idle mode bit . setting this bit activates the idle mode; see note 2.
1998 nov 02 61 philips semiconductors product speci?cation pager baseband controller pca5010 2. if logic 1s are written to pd and idl at the same time, pd takes precedence. the reset value of pcon is (00000000). 6.21 reset to initialize the pca5010 a reset is performed by either of 2 methods: applying an external reset signal to the resetin pin via the on-chip watchdog timer. the reset state of the output pins is given in separate tables (tables 2 to 6). the reset state of sfrs is given in a separate overview (see table 1). while a reset is applied to the device the output resout is driven low. the internal ram is not affected by reset. when v dd is turned on, the ram contents are indeterminate. 6.21.1 e xternal reset using the resetin pin the external reset input for the pca5010 is the resetin pin. a schmitt trigger is used at the input for noise rejection. immediately after the resetin goes high, an internal reset is executed. as a consequence the sfrs and port pins adopt their reset state, ale and psen are held high. as long as resetin pin stays high, the reset state is maintained. when resetin goes low, the device start-up sequence is executed (see section 6.22). 6.21.2 e xternal power - on reset using the resetin pin an automatic reset can be obtained by connecting the resetin pin to v bat via a capacitor and to v ss via a resistor. at power-on, the voltage on the resetin pin is equal to v bat and decreases from v bat as the capacitor charges through the resistor to v ss . v resetin must remain higher than the threshold of the schmitt trigger for a duration of t resetin (see chapter ac characteristics). the reset configuration is shown in fig.35. 6.21.3 internal r eset the watchdog which is available in the pca5010 (see section 6.16) will force a reset if it is enabled and expires. a reset is also forced, when the dc/dc converter restarts operation from off mode (see section 6.22.3). all resets to the microcontroller can be observed as negative pulses at the output resout. fig.35 application diagram for external power-on reset configuration. handbook, full pagewidth mgr344 v bat v bat v ss resetin reset and power controller internal reset for microcontroller resout pca5010 watchdog restart dc/dc converter 10 m f 10 k w
1998 nov 02 62 philips semiconductors product speci?cation pager baseband controller pca5010 6.22 dc/dc converter 6.22.1 f unction the dc/dc converter converts the voltage from a single primary cell (0.9 to 1.6 v) to a nominal 2.2 v v dd for on-chip and off-chip use. for emc reasons a special technique is used to minimize coil current ripples under all load conditions. the voltage generated by the dc/dc converter is available at pin v dd(dc) . the supply for all functions of the chip is taken from the v dd and v dda pins. the user has to connect v dd(dc) to the other v dd pins. the supply used for the reference and comparators is taken from v dda . a typical circuit configuration is shown in fig.36. for a certain current load (i l ) the controller settles to a stable voltage v dd (i l ) in the window 2.15 to 2.25 v. increasing the load decreases v dd (i l ) by a small amount. when v dd (i l ) drops below 2.15 v the dc/dc converter calculates a new set of coefficients and v dd (i l ) settles again between 2.15 and 2.25 v (see fig.45). fig.36 typical operating circuit. handbook, full pagewidth mgl458 vind v dd(dc) 2.25 v 2.15 v digital control d1 6 mhz microcontroller v ss , v ssa resetin v bat band gap bli c i 4.7 m f c o 4.7 m f v bat 0.9 to 1.6 v c1 r1 v dd v dd v dda l 470 m h pca5010
1998 nov 02 63 philips semiconductors product speci?cation pager baseband controller pca5010 6.22.2 t ypical operating characteristics the maximum power delivered by the dc/dc converter is given by equation (1). (1) r s is the total series resistance which is the sum of r bat +r ind +r sw + esr(c o ). in figs 37 and 38 the maximum available output current i l is shown as a function of v bat and r s . p o(max) v bat () 4r s ------------------- 2 the efficiency is determined by the series resistance r s and the current consumption of the converter itself. r s is the sum of the battery resistance r bat , the dc resistance srl of the coil, the on resistance of the mosfet r ds,on and the esr of the output capacitor c o . figure 39a shows the efficiency when using a 470 m h coil with a srl of 5 w and a load capacitor of 4.7 m f with an esr of 0.5 w . in fig.39b the efficiency for the same configuration is shown but with a srl of only 0.1 w . to increase efficiency for extremely low output currents, the converter should be set into standby mode (see fig.40). fig.37 maximum available output current (ma) in normal mode. handbook, full pagewidth mgr345 0.8 1 1.2 1.6 8 4 2 6 5 3 7 1.4 v bat (v) r s ( w ) 15 20 20 25 25 30 30 30 35 35 35 40 40 40 45 45 50 50 55 55 60 60 65 70 70 75 75 80 90 100 v dd = 2.2 v; r s =r bat +r ind +r sw .
1998 nov 02 64 philips semiconductors product speci?cation pager baseband controller pca5010 fig.38 maximum available output current (ma) in standby mode. handbook, full pagewidth mgr346 0.8 1 1.2 1.6 8 4 2 6 5 3 7 1.4 v bat (v) r s ( w ) 15 15 20 20 25 25 30 30 30 35 35 35 40 40 45 45 50 50 55 60 65 70 80 10 10 12.5 12.5 5 5 7.5 7.5 2 2 3.5 3.5 1 1 v dd = 2.2 v; r s =r bat +r ind +r sw . fig.39 efficiency in normal mode as a function of load current. b. r s =1 w . a. r s =6 w . handbook, halfpage 020 100 0 20 mgr134 h (%) i l (ma) 40 60 80 4 8 12 16 (2) (3) (1) handbook, halfpage 020 100 0 20 mgr135 i l (ma) 40 60 80 4 8 12 16 (2) (3) (1) h (%) (1) v bat = 1.5 v. (2) v bat = 1.2 v. (3) v bat = 0.9 v.
1998 nov 02 65 philips semiconductors product speci?cation pager baseband controller pca5010 fig.40 efficiency in standby mode as a function of load current. handbook, halfpage 012 4 100 0 i l (ma) 80 mgr136 3 60 40 20 (2) (3) (1) h (%) (1) v bat = 1.5 v. (2) v bat = 1.2 v. (3) v bat = 0.9 v. 6.22.3 start - up description 6.22.3.1 start-up from reset external rc together with an on-chip schmitt trigger is used to generate a reset pulse after the insertion of a new battery (see section 6.21). a reset pulse at the resetin pin resets the sfrs and the internal registers of the dc/dc converter to the factory programmed values and the start-up sequence shown in fig.41 is started. the reset pulse must be essentially longer then the rise time of v bat . the start-up sequence is divided into several steps: 1. start-up 76.8 khz crystal oscillator (256 clocks). 2. boost up of v dd to approximately 1.7 v using the 76.8 khz clock. during this phase, the p-channel mosfet is switched off and the charge is transferred via the external schottky diode. 3. start of the 6 mhz clock ; (see section 6.12). 2 1 76.8 khz ----------------------- ? ?? 4. boost up v dd to 2.2 v using the internal 6 mhz clock and the p-channel mosfet. as soon as v dd 3 2.15 v, the stable flag is set to indicate that the system is powered up successfully and the microcontroller starts operation. the dc/dc converter now stays in the normal operating mode. if a reset pulse is generated during normal operation, the dc/dc converter immediately resets the whole system and enters the start-up sequence. 6.22.3.2 start-up from off mode start-up from off mode behaves exactly as start-up from external reset (see fig.41) except that: the internal registers of the dc/dc converter are not reset; however the dc/dc converter sfrs are reset. off mode is exited when one of the following events occur: key pressed minute interrupt wake-up interrupt.
1998 nov 02 66 philips semiconductors product speci?cation pager baseband controller pca5010 fig.41 system power-up/off sequencing. handbook, full pagewidth mgr137 wait until v dd > 2.2 v ( < 1 ms) wait until v dd > 1.7 v (up to some ms) delay = 2t dc/dc uses 6 mhz start dc/dc using 76.8 khz clock stable = 1 v dd ok = 1 delay = 256t reset internal register dc/dc: v dd set to v bat v dd ok = 0 delay = 15t v dd ok = 0 stable = 0 dc/dc converter microcontroller resetin restart = norm off standby init reset operating watchdog expires keys or wake-up or minute or watchdog reset resout active z_r active resout active normal operation mode microcontroller sets off bit in dccon0 sfr (t = period of xtl1 input signal)
1998 nov 02 67 philips semiconductors product speci?cation pager baseband controller pca5010 6.22.4 d escription of operating modes 6.22.4.1 normal operating mode once the system is powered-up successfully (stb = 1), the dc/dc converter is in normal operating mode. this mode has two sub modes: normal mode standby mode. by setting/resetting the standby bit in dccon0 (d1h), the dc/dc converter switches between normal mode and standby mode. switching between these two modes is possible at any time by software if the controller is in normal operating mode. normal operating mode can be exited by any of the following events: high level at the resetin pin a watchdog reset, which will force the same sequence as an off command writing the off bit in dccon0. setting the off bit in dccon0 forces the converter into dc/dc converter off mode. 6.22.4.2 normal mode normal mode is the high efficiency mode of the dc/dc converter. in this mode the controller can keep v dd stable at 2.2 v up to the maximum available current (see fig.37). the output voltage is regulated in a small window and the current peaks in the coil are kept as small as possible (see fig.45). after a reset and the following start-up sequence, the controller is in normal mode. to shorten the settling time when the receiver is switched on or off, the dc/dc converter uses 2 sets of coefficients. one for low output current and one for high output current. when the rxe bit in dccon0 is set, the dc/dc converter stores the actual coefficients for low output current and switches to the coefficients for high load current. at the same time the receiver should be enabled. when the battery voltage did not change very much since the last time the receiver was on, the settling time is only a few microseconds instead of a few hundreds of microseconds when not using the rxe bit. when switching off the receiver, the rxe bit in dccon0 should be reset. in this case, the dc/dc converter stores the new values for high output current and restores the values for low output current. it should be noted that the rxe bit does not change the algorithm of the dc/dc converter but shortens the settling time dramatically. when the load is so high that the required output current cannot be delivered, the dc/dc converter resets the signal stb and a dc/dc interrupt is issued to the processor via irq sfr irq1.5. stb = 0 flags the inability to deliver enough current in normal mode or in standby mode. when the stb flag is set to logic 0, v dd can drop very quickly, depending on the battery voltage and the load. 6.22.4.3 standby mode standby mode is a low current mode which can be used when only the microcontroller is running and the quality of v dd is not important. in standby mode the dc/dc converter uses the 76.8 khz clock instead of the 6 mhz clock. this reduces the current consumption of the dc/dc converter. the maximum output current in this mode is limited to a few milliamps (see fig.38). in standby mode v dd can be set to 1.9, 2.0, 2.1 or 2.2 v by setting the vlo1 and vlo0 bits in dccon1 to the corresponding values. when the load is so high that the required output current cannot be delivered, the dc/dc converter resets the signal stb and a dc/dc interrupt is issued to the processor via irq sfr irq1.5. in this case, the microcontroller should switch off the different loads and switch to normal mode. 6.22.4.4 off mode off mode can only be entered by setting the off bit in dccon0 by software. the dc/dc converter waits for 15 periods of the 76.8 khz clock before it sets v dd to v bat and switches off completely (see fig.41). in the off mode the pmos is conducting and therefore it is guaranteed that v dd never drops below v bat - 100 mv. when the dc/dc converter is in off mode, one of the following events can restart the converter: p1x (independent from interrupt enabling or polarity) minute wake-up resetin pulse.
1998 nov 02 68 philips semiconductors product speci?cation pager baseband controller pca5010 6.22.5 v oltage / current ripple the ripples are determined by v bat , inductance l, c o , esr (equivalent series resistance of c o , switching frequency and the load current i l . the ripples are illustrated in fig.43. if esr = 0 w , then v ripple = d v. fig.42 circuit to analyse ripples. handbook, full pagewidth mgr138 d1 p n c i v bat c o esr i l v dd l v c i l fig.43 zoom in on the voltage and current ripples. handbook, full pagewidth mgr139 v dd t sw t n t p v ripple i ripple d v i l i mean t t t n i l i mean i peak t
1998 nov 02 69 philips semiconductors product speci?cation pager baseband controller pca5010 table 54 ripples in normal operation mode 6.22.6 s witching frequencies depending on the load and more importantly on the battery voltage the controller uses different on and off-times for the nmos and pmos transistors. this results in different switching frequencies. if the 6 mhz ring oscillator is trimmed to 6 mhz (see section 6.12) the switching frequency is 120 khz f sw 400 khz. a typical frequency behaviour is shown in fig.44. mode standby norm t n = 6.51 m st n = 1, 2 or 4 m s 0.2 d p 0.73 t n = 6.51 m st n = 1, 2 or 4 m s t n = 6.51 m st n = 1, 2 or 4 m s i peak v bat t n l --- - = i ripple v bat t n l --- - = i lmean i l d p ------ - = d v i l t n c o -------------- - = d v i l t n c o -------------- - = v ripple v bat t n l ----------------------- esr = v ripple i mean 1 2 -- - v bat t n l ----------------------- + ? ?? esr = fig.44 switching frequencies. l = 470 m h, srl = 5 w , c o = 4.7 m f, esr = 0.5 w . (1) v bat = 1.5 v. (2) v bat = 1.2 v. (3) v bat = 1.0 v. handbook, halfpage 0 400 300 200 100 420 i l (ma) f sw (khz) (1) mgr140 81216 (2) (3)
1998 nov 02 70 philips semiconductors product speci?cation pager baseband controller pca5010 fig.45 v dd as a function of load current. v bat = 1.2 v; l = 470 m h; srl = 5 w ; c o = 4.7 m f; esr = 0.5 w . handbook, full pagewidth mgr141 2.25 2.20 2.15 2.10 v dd (i l ) mean 4 0 8 12 16 20 i l (ma) v dd (v) hf ripple 6.22.7 v dd adjustment v dd can be shifted in four steps by adjusting the band gap voltage. the band gap voltage is set with the two bits vbg1 and vbg0 in dccon1 according to table 55. table 55 v dd adjustment vbg1 vbg0 output voltage 00v dd 01v dd - 50 mv 10v dd +50mv 11v dd + 100 mv 6.22.8 b attery low measurement battery low measurement is enabled by setting the sbli bit in dccon0. 0.5 ms after setting sbli to logic 1 the bli bit in dccon0 contains the measurement result. when bli = 0 the battery voltage is below 1.1 v. when bli = 1 v bat is above 1.1 v. when sbli = 1 v bat is measured continuously. setting sbli to logic 0 disables the v bat comparator and bli is set to logic 1. after a reset pulse at resetin, sbli is reset to logic 0.
1998 nov 02 71 philips semiconductors product speci?cation pager baseband controller pca5010 6.22.9 dc/dc c ontrol r egister (dccon0) the dccon0 special function register is used to control the operation of the on-chip dc/dc converter. table 56 dc/dc control register (dccon0, sfr address d1h) table 57 description of the dccon0 bits 76543210 off sby rxe sbli -- stb bli bit symbol function dccon0.7 off writing this sfr bit to logic 1 puts the dc/dc converter in the off mode (independent of other control bits). dccon0.6 sby writing this sfr bit to logic 1 puts the dc/dc converter in the standby mode, where the dc/dc converter is clocked from the 76.8 khz oscillator and the ripple voltage will be higher. if the dc/dc converter is unable to deliver enough current in sby mode, the software has to reset the sby mode. dccon0.5 rxe writing this sfr bit to logic 1 uses the stored set of coef?cients from a local register to force the dc/dc converter into the state which is appropriate for the required current. the contents of this local register are maintained when the dc/dc converter is set into off state. for the ?rst time after connecting v bat a set of default coef?cients is used. writing this bit to logic 0 copies the actual coef?cients used momentary by the dc/dc converter back to the local register. dccon0.4 sbli writing this sfr bit to logic 1 enables the circuitry for measurement of the battery voltage. the new bli value is valid 0.5 ms later. in order to make a new measurement, the receiver should draw current (continuous mode of dc/dc converter). if sbli is logic 0 (bli measurement disabled) bli will go to high. dccon0.3 - unused. dccon0.2 - unused. dccon0.1 stb set by the dc/dc converter after power-up . reset by dc/dc converter if the converter is not able to deliver the required power. the signal is set in sby and non sby mode. this bit is read only. dccon0.0 bli battery low indicator . set by dc/dc converter if v bat < 1100 mv 50 mv. this bit is read only.
1998 nov 02 72 philips semiconductors product speci?cation pager baseband controller pca5010 6.22.10 dc/dc a djust c ontrol r egister (dccon1) the dccon1 special function register is used to adjust the exact voltage levels of the on-chip dc/dc converter. table 58 dc/dc adjust control register (dccon1 and sfr address d2h) table 59 description of the dccon1 bits 7 instruction set the pbb family uses a powerful instruction set which permits the expansion of on-chip cpu peripherals and optimizes power consumption in idle and active modes as well as byte efficiency and execution speed. typical execution times and energy consumption at a v dd of 2.2 v are given in table 60. attention : for most opcodes the numbers for execution speed and energy are also strongly dependant on the data (add, subb, dec, inc, mul, div, da, conditional jumps etc.) and the operand address (cpu internal sfrs or sfrs in a peripheral block). table 60 instruction set 76543210 vbg1 vbg0 vlo1 vlo0 ---- bit symbol function dccon1.7 vbg1 adjust for band gap voltage ; used to trim the band gap voltage [00] = 1.260 v, [01] = 1.233 v, [10] = 1.286 v, [11] = 1.312 v. dccon1.6 vbg0 dccon1.5 vlo1 adjust for dc/dc converter output voltage in standby mode ; [00] = 1.9 v, [01] = 2.0 v, [10] = 2.1 v, [11] = 2.2 v. dccon1.4 vlo0 dccon1.3 - unused dccon1.2 - unused dccon1.1 - unused dccon1.0 - unused mnemonic description bytes exec. time [ m s] energy [nj] opcode (hex) arithmetic operations add a,rn add register to a 1 0.498 1.831 2* add a,direct add direct byte to a 2 0.631 2.501 25 add a,@ri add indirect ram to a 1 0.529 1.990 26, 27 add a,#data add immediate data to a 2 0.583 2.262 24 addc a,rn add register to a with carry ?ag 1 0.508 1.864 3* addc a,direct add direct byte to a with carry ?ag 2 0.637 2.525 35 addc a,@ri add indirect ram to a with carry ?ag 1 0.539 2.030 36, 37 addc a,#data add immediate data to a with carry ?ag 2 0.597 2.304 34 subb a,rn subtract register from a with borrow 1 0.497 1.861 9* subb a,direct subtract direct byte from a with borrow 2 0.630 2.527 95 subb a,@ri subtract indirect ram from a with borrow 1 0.528 2.021 96, 97 subb a,#data subtract immediate data from a with borrow 2 0.582 2.287 94 inc a increment a 1 0.459 2.475 04
1998 nov 02 73 philips semiconductors product speci?cation pager baseband controller pca5010 inc rn increment register 1 0.457 1.737 0* inc direct increment direct byte 2 0.586 1.982 05 inc @ri increment indirect ram 1 0.493 1.982 06, 07 dec a decrement a 1 0.459 1.489 14 dec rn decrement register 1 0.457 1.74 1* dec direct decrement direct byte 2 0.590 2.488 15 dec @ri decrement indirect ram 1 0.489 1.972 16, 17 inc dptr increment data pointer 1 0.384 1.345 a3 mul ab multiply a and b 1 0.378 1.242 a4 div ab divide a by b 1 0.733 2.532 84 da a decimal adjust a 1 0.426 1.363 d4 logic operations anl a,rn and register to a 1 0.495 1.857 5* anl (1) a,direct and direct byte to a 2 0.623 2.494 55 anl a,@ri and indirect ram to a 1 0.525 2.021 56, 57 anl a,#data and immediate data to a 2 0.583 2.272 54 anl direct,a and a to direct byte 2 0.650 2.639 52 anl direct,#data and immediate data to direct byte 3 0.719 3.138 53 orl a,rn or register to a 1 0.459 1.605 4* orl (1) a,direct or direct byte to a 2 0.584 2.248 45 orl a,@ri or indirect ram to a 1 0.486 1.767 46, 47 orl a,#data or immediate data to a 2 0.539 2.015 44 orl direct,a or a to direct byte 2 0.614 2.405 42 orl direct,#data or immediate data to direct byte 3 0.679 2.886 43 xrl a,rn exclusive-or register to a 1 0.459 1.715 6* xrl (1) a,direct exclusive-or direct byte to a 2 0.584 2.361 65 xrl a,@ri exclusive-or indirect ram to a 1 0.486 1.873 66, 67 xrl a,#data exclusive-or immediate data to a 2 0.540 2.128 64 xrl direct,a exclusive-or a to direct byte 2 0.614 2.550 62 xrl direct,#data exclusive-or immediate data to direct byte 3 0.679 3.017 63 clr a clear a 1 0.374 1.265 e4 cpl a complement a 1 0.398 1.511 f4 rl a rotate a left 1 0.383 1.388 23 rlc a rotate a left through the carry ?ag 1 0.383 1.390 33 rr a rotate a right 1 0.382 1.381 03 rrc a rotate a right through the carry ?ag 1 0.383 1.382 13 swap a swap nibbles within a 1 0.371 1.394 c4 mnemonic description bytes exec. time [ m s] energy [nj] opcode (hex)
1998 nov 02 74 philips semiconductors product speci?cation pager baseband controller pca5010 data transfer mov a,rn move register to a 1 0.377 1.406 e* mov a,direct move direct byte to a 2 0.509 2.080 e5 mov a,@ri move indirect ram to a 1 0.408 1.568 e6, e7 mov a,#data move immediate data to a 2 0.426 1.752 74 mov rn,a move a to register 1 0.344 1.347 f* mov rn,direct move direct byte to register 2 0.602 2.654 a* mov rn,#data move immediate data to register 2 0.415 1.839 7* mov direct,a move a to direct byte 2 0.477 2.024 f5 mov direct,rn move register to direct byte 2 0.536 2.294 8* mov direct,direct move direct byte to direct byte 3 0.661 2.950 85 mov direct,@ri move indirect ram to direct byte 2 0.564 2.438 86, 87 mov direct,#data move immediate data to direct byte 3 0.679 3.017 75 mov @ri,a move a to indirect ram 1 0.378 1.517 f6, f7 mov @ri,direct move direct byte to indirect ram 2 0.633 2.629 a6, a7 mov @ri,#data move immediate data to indirect ram 3 0.448 2.019 76, 77 mov dptr,#data 16 load data pointer with a 16-bit constant 3 0.519 2.267 90 movc a,@a+dptr move code byte relative to dptr to a 1 0.775 3.570 93 movc a,@a+pc move code byte relative to pc to a 1 0.770 3.374 83 movx a,@ri move external ram (8-bit address) to a 1 0.707 2.732 e2, e3 movx a,@dptr move external ram (16-bit address) to a 1 0.710 2.605 e0 movx @ri,a move a to external ram (8-bit address) 1 0.629 2.595 f2, f3 movx @dptr,a move a to external ram (16-bit address) 1 0.631 2.439 f0 push direct push direct byte onto stack 2 0.600 2.543 c0 pop direct pop direct byte from stack 2 0.606 2.548 d0 xch a,rn exchange register with a 1 0.513 1.847 c* xch a,direct exchange direct byte with a 2 0.645 2.526 c5 xch a,@ri exchange indirect ram with a 1 0.544 2.024 c6, c7 xchd a,@ri exchange low-order nibble indirect ram with a 1 0.486 1.904 d6, d7 boolean variable manipulation clr c clear carry ?ag 1 0.293 1.075 c3 clr bit clear direct bit 2 0.597 2.509 c2 setb c set carry ?ag 1 0.293 1.084 d3 setb bit set direct bit 2 0.611 2.603 d2 cpl c complement carry ?ag 1 0.320 1.134 b3 cpl bit complement direct bit 2 0.583 2.471 b2 anl c,bit and direct bit to carry ?ag 2 0.540 2.187 82 anl c,/bit and complement of direct bit to carry ?ag 2 0.563 2.388 b0 mnemonic description bytes exec. time [ m s] energy [nj] opcode (hex)
1998 nov 02 75 philips semiconductors product speci?cation pager baseband controller pca5010 notes 1. this opcode works in a slightly different way to a standard 80c51 cpu. if the direct field addresses one of the i/o ports (p0 to p3) then the standard 80c51 uses the port pin input state for the operation while the pca5010 uses the sfr contents. 2. this opcode works in a slightly different way to a standard 80c51 cpu. if the direct bit field addresses one of the port bits, then the state of the corresponding port pin is written to the port sfr after execution of the instruction. orl (2) c,bit or direct bit to carry ?ag 2 0.561 2.341 72 orl c,/bit or complement of direct bit to carry ?ag 2 0.561 2.341 a0 mov c,bit move direct bit to carry ?ag 2 0.610 2.542 a2 mov bit,c move carry ?ag to direct bit 2 0.610 2.542 92 program and machine control acall addr11 absolute subroutine call 2 0.840 3.384 1 addr lcall addr16 long subroutine call 3 1.082 4.562 12 ret return from subroutine 1 1.082 4.562 22 reti return from interrupt 1 1.082 4.562 32 ajmp addr11 absolute jump 2 0.670 2.524 1 addr ljmp addr16 long jump 3 0.840 3.384 02 sjmp rel short jump (relative address) 2 0.670 2.524 80 jmp @a+dptr jump indirect relative to the dptr 1 1.049 4.015 73 jz rel jump if a is zero 2 0.639 2.224 60 jnz rel jump if a is not zero 2 0.754 2.896 70 jc rel jump if carry ?ag is set 2 0.620 2.128 40 jnc rel jump if carry ?ag is not set 2 0.733 2.705 50 jb bit,rel jump if direct bit is set 3 0.788 3.095 20 jnb bit,rel jump if direct bit is not set 3 0.902 3.708 30 jbc bit,rel jump if direct bit is set and clear bit 3 0.894 3.520 10 cjne a,direct,rel compare direct to a and jump if not equal 3 0.855 3.307 b5 cjne a,#data,rel compare immediate to a and jump if not equal 3 0.794 3.024 b4 cjne rn,#data,rel compare immediate to register and jump if not equal 3 0.787 3.139 b* cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 0.822 3.333 b6, b7 djnz rn,rel decrement register and jump if not zero 2 0.857 3.474 d* djnz direct,rel decrement direct and jump if not zero 3 0.991 4.178 d5 nop no operation 1 0.284 1.027 00 mnemonic description bytes exec. time [ m s] energy [nj] opcode (hex)
1998 nov 02 76 philips semiconductors product speci?cation pager baseband controller pca5010 table 61 notation for data addressing modes table 62 hexadecimal opcode cross-reference symbol description rn working registers r0 to r7 direct 128 internal ram locations and any special function register (sfr). @ri indirect internal ram location addressed by register r0 or r1 #data 8-bit constant included in instruction #data 16 16-bit constant included as bytes 2 and 3 of instruction bit direct addressed bit in internal ram or sfr addr16 16-bit destination address. used by lcall and ljmp. the branch will be anywhere within the 64 kbytes program memory address space. addr11 11-bit destination address. used by acall and ajmp. the branch will be within the same 2-kbyte page of program memory as the ?rst byte of the following instruction. rel signed (two's complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is - 128 to +127 bytes relative to ?rst byte of the following instruction. symbol description * 8, 9, a, b, c, d, e and f 11, 31, 51, 71, 91, b1, d1 and f1 01, 21, 41, 61, 81, a1, c1 and e1
1998 nov 02 77 philips semiconductors product speci?cation pager baseband controller pca5010 7.1 instruction map handbook, full pagewidth first hexadecimal character of opcode movc a,@a+dptr second hexadecimal character of opcode 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123 456 789abcdef nop jbc bit,rel jb bit,rel jnb bit,rel jc rel jnc rel jz rel jnz rel sjmp rel mov dptr,#data 16 orl c,/bit anl c,/bit push direct pop direct movx a,@dptr movx @dptr,a ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ajmp addr11 acall addr11 ljmp addr16 lcall addr16 ret reti orl direct,a anl direct,a xrl direct,a orl c,bit anl c,bit mov bit,c mov c,bit cpl bit clr bit setb bit 01 01 movx @ri,a movx a,@ri rr a rrc a rlc a orl direct,#data anl direct,#data xrl direct,#data jmp @a+dptr movc a,@a+pc inc dptr cpl c clr c setb c rl a inc a dec a add a,#data addc a,#data orl a,#data anl a,#data xrl a,#data mov a,#data div ab subb a,#data mul ab cjne a,#data,rel swap a da a clr a cpl a inc direct dec direct add a,direct addc a,direct orl a,direct anl a,direct xrl a,direct mov direct,#data mov direct,direct subb a,direct cjne a,direct,rel xch a,direct djnz direct,rel mov a,direct mov direct,a * 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 0 101 2 34567 inc@ri dec@ri add a,@ri addc a,@ri orl a,@ri anl a,@ri xrl a,@ri mov @ri,#data mov direct,@ri subb a,@ri mov @ri,direct cjne @ri,#data,rel xch a,@ri xchd a,@ri mov a,@ri mov @ri,a inc rn dec rn add a,rn addc a,rn orl a,rn anl a,rn xrl a,rn mov direct,rn subb a, rn mov rn,direct cjne rn,#data,rel xch a,rn djnz rn,rel mov a,rn mov rn,a mov rn,#data * mov a, acc is not a valid instruction. mgl457
1998 nov 02 78 philips semiconductors product speci?cation pager baseband controller pca5010 8 limiting values according to the absolute maximum ratings system (iec 134); note 1. note 1. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise specified. 9 external components symbol parameter min. max. unit v bat battery supply voltage - 0.5 +2.0 v v dd supply voltage - 0.5 +5.0 v v i input voltage (all inputs) - 0.3 v dd + 0.3 v i i/o maximum sink/source current for all input/output pins - 10 +10 ma i bat , i ind maximum supply current for pins v bat and vind - 100 ma i dd maximum supply current for any supply pin - 50 ma p tot total power dissipation - 100 mw v esd(hbm) maximum esd stress level applied to v pp pin using human body model - 2000 v v esd(mm) maximum esd stress level applied to v pp pin using machine model - 200 v t stg storage temperature - 55 +125 c t amb operating ambient temperature (for all devices) - 10 +55 c symbol parameter min. typ. max. unit discrete components l inductor 330 470 1000 m h c o output capacitor - 4.7 10.0 m f r fb feedback oscillator resistance 2.0 2.2 - m w r x1 parasitic serial resistance of quartz -- 20 k w
1998 nov 02 79 philips semiconductors product speci?cation pager baseband controller pca5010 10 dc characteristics v ss =0v; v dd = 2.2 v; v bat = 1.2 v; t amb = - 10 to +55 c; all voltages referenced to v ss unless otherwise speci?ed; dc/dc converter con?gured as indicated in note 1. symbol parameter conditions min. typ. max. unit battery supply v bat battery operating voltage note 2 0.9 1.2 1.6 v i bat(reset) static reset supply current v bat = 1.2 v; pin resetin at v bat ; xtl1 at v ss ; p1.6, p1.7; i, q, ea, tclk, v pp at v ss or v dd ; all outputs and i/os open-circuit - 0.5 5 m a i dd(reset) static reset supply current v dd = 2.2 v; pin resetin at v bat ; xtl1 at v ss ; p1.6, p1.7, i, q, ea, tclk, v pp at v ss or v dd ; all outputs and i/os open-circuit - 0.5 10 m a r nfet nfet pin-to-pin resistance t amb =25 c; v dd = 2.2 v; note 3 - 1.1 2 w r pfet pfet pin-to-pin resistance t amb =25 c; v dd = 2.2 v; note 3 - 1.2 2 w i l(nfet) nfet leakage current -- 1 m a i l(pfet) pfet leakage current - 1 --m a i nfet(max) maximum allowed nfet current -- 50 ma i pfet(max) maximum allowed pfet current -- 50 ma dc/dc converter in off mode v dd dc supply voltage output v bat - 0.1 - v bat v i bat(off) current consumed from v bat by the dc/dc converter itself v dd =v bat ; all inputs at v ss or v dd ; all outputs and i/os open-circuit - 6 -m a dc/dc converter in standby mode v dd dc supply voltage generated by the on-chip dc/dc converter for the pca5010 and external chips note 4; programmable in 4 steps 1.8 1.9 2.3 v 1.9: [vlo, vlo] = 00 - 1.9 - v 2.0: [vlo, vlo] = 01 - 2.0 - v 2.1: [vlo, vlo] = 10 - 2.1 - v 2.2: [vlo, vlo] = 11 - 2.2 - v v drop dc voltage drop due to load i l = 500 m a; notes 4 and 5 -- 100 mv v ripple(p-p) ripple voltage (peak-to-peak value) notes 5 and 6 - 50 - mv
1998 nov 02 80 philips semiconductors product speci?cation pager baseband controller pca5010 i bat(stb) current consumed from v bat by the dc/dc converter itself t amb =25 c; notes 7 and 8 - 25 -m a i dd(max)(stb) maximum delivered continuous supply current v bat = 0.9 v; r s =8 w ; notes 8 and 9; see fig.38 1 -- ma h (stb) ef?ciency of dc/dc converter in standby mode v bat = 1.2 v; i dd = 100 m a; note 8 - 80 - % dc/dc converter in high current mode (non standby) v dd dc supply voltage generated by the on-chip dc/dc converter for the pca5010 and external chips note 4 2.2 - 6% 2.2 2.2 + 6% v v dd(av) mean dc voltage notes 4 and 5 2.1 2.2 2.3 v v hfripple(p-p) ripple voltage for frequencies above 20 khz (peak-to-peak value) notes 5 and 8 -- 100 mv v lfripple(p-p) low frequency ripple voltage caused by load variations (peak-to-peak value) notes 3, 5 and 8 -- 100 mv i bat(norm) current consumed from v bat by the dc/dc converter itself t amb =25 c; notes 8 and 10; see fig.51 - 110 -m a i dd(max) maximum delivered supply current v bat = 0.9 v; r s = 8 w ; notes 8 and 9; see fig.37 10 -- ma v bat = 1.0 v; r s = 5 w ; notes 8 and 9 20 -- ma h (norm) ef?ciency of dc/dc converter note 8 v bat 3 1.2 v; i dd =3ma - 90 - % v bat 3 1.2 v; i dd =10ma - 85 - % v bat = 0.9 v; i dd =3ma - 85 - % v bat = 0.9 v; i dd =10ma - 75 - % external supply current from v dd = 2.2 v and v bat = 1.2 v v dd dc supply voltage (v dd and v dda pins) note 11; see fig.64 2.2 2.2 2.5 v i bat operating battery current t amb =25 c; 76.8 khz quartz - 2 -m a i dd(stb) operating standby mode supply current from v dd t amb =25 c; note 7 - 12 -m a symbol parameter conditions min. typ. max. unit
1998 nov 02 81 philips semiconductors product speci?cation pager baseband controller pca5010 i dd(rx) operating receive mode supply current from v dd t amb =25 c; note 10 - 85 -m a supply current from internal or external v dd = 2.2 v i dd(micro) i dd due to operation of microcontroller t amb =25 c; note 12 - 0.7 - ma/mips i dd(uart) increase in i dd due to operation of the uart t amb =25 c - 5 -m a i dd(iic) increase in i dd due to operation of the i 2 c-bus master t amb =25 c - 20 -m a i dd(t0) increase in i dd due to operation of timer/counter0 t amb =25 c - 0 -m a i dd(t1) increase in i dd due to operation of timer/counter1 t amb =25 c - 2 -m a i dd(afc) supply current due to operation of afc-dac t amb =25 c - 60 -m a i dd(sbli) supply current due to battery measurement active (sbli = 1) t amb =25 c - 20 -m a i dd(6mhz) increase in i dd due to activation of 6 mhz oscillator in standby mode t amb =25 c; frequency adjusted to 6 mhz - 50 -m a otp programming (otp data retention can only be guaranteed if the devices are preprogrammed by philips semiconductors; data retention cannot be guaranteed for customer programmed samples) v dd(prog) supply voltage during programming note 11 2.2 - 3.6 v v pp program supply voltage 12.5 - 13 v i pp program supply current note 13 - 24 - ma t amb(prog) operating ambient temperature during programming 21 - 27 c band gap (reference voltage for all comparators) v bg band gap voltage [vbg1, vbg0] = 00 1.23 1.26 1.29 v [vbg1, vbg0] = 01 - 1.233 - v [vbg1, vbg0] = 10 - 1.286 - v [vbg1, vbg0] = 11 - 1.312 - v initial v dd ok detection v dd(ok) v dd ok indication t amb =25 c 1.5 1.85 2.0 v battery low indicator v bli battery low indication [vbg1, vbg0] = 00 1.05 1.1 1.15 v symbol parameter conditions min. typ. max. unit
1998 nov 02 82 philips semiconductors product speci?cation pager baseband controller pca5010 digital input pins i(d1), q(d0) and tclk v il low-level input voltage -- 0.2v dd v v ih high-level input voltage 0.8v dd -- v i l leakage current v i =v dd or v ss - 0.1 - 0.1 m a digital input pin resetin v il input low level -- 0.2v bat v v ih input high level 0.8v bat -- v i l leakage current v i =v dd or v ss - 0.1 - 0.1 m a digital input/output pin ea v il low-level input voltage output not sinking current -- 0.2v dd v v ih high-level input voltage output not sinking current 0.8v dd -- v i (o)sink output sink current v dd = 2.2 v; v i = 0.4 v 0.75 -- ma i (o)source output source current v dd = 2.2 v; v i =v dd - 0.4 v --- 0.75 ma i nmos(h) nmos hold current v dd = 2.2 v; v i = 0.6 v -- 200 m a i pmos(h) pmos hold current v dd = 2.2 v; v i =v dd - 0.6 v - 200 --m a digital output pin resout i (o)sink output sink current v dd = 2.2 v; v i = 0.4 v 1.5 -- ma i (o)source output source current v dd = 2.2 v; v i =v dd - 0.4 v --- 1.5 ma digital input/output pins psen v il low-level input voltage output not sinking current -- 0.2v dd v v ih high-level input voltage output not sinking current 0.8v dd -- v i (o)sink output sink current v dd = 2.2 v; v i = 0.4 v 0.75 -- ma i (o)source output source current v dd = 2.2 v; v i =v dd - 0.4 v --- 0.75 ma i pu weak pull-up current v dd = 2.2 v; v i =0v - 20 - 7 - 2 m a digital input/output pins ale v il low-level input voltage output not sinking current -- 0.2v dd v v ih high-level input voltage output not sinking current 0.8v dd -- v i (o)sink output sink current v dd = 2.2 v; v i = 0.4 v 1.5 -- ma i (o)source output source current v dd = 2.2 v; v i =v dd - 0.4 v --- 1.5 ma i pu weak pull-up current v dd = 2.2 v; v i =0v - 20 - 7 - 2 m a microcontroller input/output ports p0, p1 and p2 pins (except p1.6 and p1.7) v il low-level input voltage output not sinking current -- 0.2v dd v v ih high-level input voltage output not sinking current 0.8v dd -- v i (o)sink output sink current v dd = 2.2 v; v i = 0.4 v 0.75 -- ma symbol parameter conditions min. typ. max. unit
1998 nov 02 83 philips semiconductors product speci?cation pager baseband controller pca5010 i (o)source output source current v dd = 2.2 v; v i =v dd - 0.4 v --- 0.75 ma i pu weak pull-up current v dd = 2.2 v; v i =0v - 20 - 7 - 2 m a i pmos(h) pmos hold current v dd = 2.2 v; v i =v dd /2 - 200 - 70 - 20 m a microcontroller output port p3 pins i (o)sink output sink current v dd = 2.2 v; v i = 0.6 v 4 -- ma i (o)source output source current v dd = 2.2 v; v i =v dd - 0.6 v --- 6ma open drain pins sda and scl (p1.6 and p1.7) v il low-level input voltage output not sinking current -- 0.2v dd v v ih high level input voltage output not sinking current 0.8v dd -- v i l leakage current v i =v dd - 1 - +1 m a i sink(stat) static output sink current v dd = 2.2 v; v i = 0.4 v 2.25 -- ma i sink(stat)(sc) static output sink short-circuit current v dd = 2.2 v; v i =v dd 2.2 6 14 ma at output pin i (o)sink output sink current v dd = 2.2 v; v i = 0.4 v 3 -- ma i (o)source output source current v dd = 2.2 v; v i =v dd - 0.4 v --- 3ma 76.8 khz oscillator v il(xtl1) low-level input voltage xtl1 -- 0.3 v v ih(xtl1) high-level input voltage xtl1 1 -- v i li(xtl1) leakage current at xtl1 v i =v bat or v ss - 1 - +1 m a i bias bias current from xtl2 to v ss v bat = 1.6 v; xtl1 at v ss 0.5 0.8 1.1 m a i op operating current consumption v bat = 1.6 v; r fb = 2.2 m w - 2 -m a g m transconductance i o = 0.3 m a 5 20 60 m a/v v wp dc working point - 550 - mv afc-dac v afc resolution - 1 64 v dd - v d afc deviation for codes between 010000 and 100000 from straight line - 0.25lsb - +0.25lsb r l(dac) allowed resistive load at dac output 10 -- k w symbol parameter conditions min. typ. max. unit
1998 nov 02 84 philips semiconductors product speci?cation pager baseband controller pca5010 notes 1. dc/dc converter configured with inductor of l = 470 m h, srl = 5 w , input capacitance of c i = 4.7 m f, esr = 0.5 w , v dd output capacitor c o = 4.7 m f, esr = 0.5 w , r bat <1 w . 2. the required v bat for starting the circuit after connecting it to the battery is 1.1 v. but once in place, the battery can be used until it is discharged to 0.9 v. 3. this parameter is not tested during production; it is guaranteed by design. 4. this parameter is not tested during production; it is covered by other measurements. 5. the accuracy of the voltage is defined by maximum offset and ripple voltage. dc offset is defined by the accuracy of the internal band gap reference and the offset of comparators, whereas the ripple voltage is defined by the limits of the allowed voltage window of the regulated v dd . 6. the ripple in standby mode is defined by v bat , l, t n and esr (see table 54). 7. pca5010 set to standby mode by software: 76.8 khz oscillator running, dc/dc converter running in standby mode, all timer/counters disabled except rtc, microcontroller idle, all outputs open-circuit, no i dd delivered to external circuits. 8. this parameter depends on external components and is not tested during production; hence no guarantee. 9. r s = total series resistance = r bat +srl+r ds(on) + esr. 10. pca5010 set to receive mode by software: 76.8 khz and 6 mhz oscillator running, dc/dc converter running in normal mode, wake-up counter, clock compensation, watchdog timer, t0 and t1 enabled, demodulator set to direct input data, afc disabled, microcontroller idle, all outputs open-circuit, no i dd delivered to external circuits. 11. the minimum supply voltage is determined by the start-up sequence of the device. when the start-up sequence is completed, the supply voltage can be lowered to 1.8 v. 12. the microcontroller operates with approximately 1.9 million instructions per second at a v dd = 2.2 v. the current consumption at this v dd is 0.7 ma/mips (peripheral blocks as e.g. timers, dc/dc converter, i 2 c-bus, uart, demodulator etc., are excluded). the current required from v dd is then 1.35 ma (typ.). this scales to sunk from v bat . 13. in mass program mode the current can increase to 100 ma. c l(dac) allowed capacitive load at dac output -- 50 pf i source(dac) afcout source current v dd = 2.2 v; v afcout =v dd - 0.4 v; code = 111111 -- 895 - 100 m a i sink(dac) afcout sink current v dd = 2.2 v; v afcout = 0.4 v; code = 000000 10 25 -m a symbol parameter conditions min. typ. max. unit i bat v dd v bat ------------ i dd 2.5 ma ==
1998 nov 02 85 philips semiconductors product speci?cation pager baseband controller pca5010 11 ac characteristics v bat = 0.9 to 1.6 v; v ss =0v; t amb = - 10 to +55 c; all voltages referenced to v ss unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit dc/dc converter; see note 1 t on turn on time off to normal operation; i l < 500 m a; note 2 -- 5ms t ch(mode) mode change time enable to standby and reverse; note 2 -- 1ms t step load step accommodation delay until stable load step from 10 m a to 6 ma; note 3 -- 1ms f sw switching frequency in normal mode; note 2 120 250 400 khz t sw switching period in standby mode; note 4 1 or 1.5 t xtl1 --m s t ch(l) inductor charge time in standby mode; note 4 - 0.5 or 1 t xtl1 -m s reset signal t resetin(min) minimum duration of resetin pulse 20 --m s microcontroller t instr(int) internal instruction execution time internal access, v dd = 2.2 v; t amb =25 c; note 5 - 550 - ns t instr(ext) external instruction execution time external access, v dd = 2.2 v; t amb =25 c; note 5 - 650 - ns 76.8 khz oscillator f xtal crystal frequency note 3 76784 76800 76816 hz f i(max) maximum input frequency through input buffer -- 100 khz c 1 input capacitance - 10 15% - pf c 2 output capacitance - 10 15% - pf 6 mhz oscillator f i(osc) oscillator input frequency [ sf4, sf3, sf2, sf1, sf0] = 00000 (reset condition) 3 5.4 8 mhz [ sf4, sf3, sf2, sf1, sf0] = 10000 1 2.7 5 mhz [ sf4, sf3, sf2, sf1, sf0] = 01111 6 7.6 11 mhz f i(osc) d f adjusted frequency 5.85 6 6.15 mhz t d(en) enable oscillator delay note 2 - 20 30 m s
1998 nov 02 86 philips semiconductors product speci?cation pager baseband controller pca5010 notes 1. dc/dc converter configured with inductor of l = 470 m h, srl = 5 w , input capacitance of c i = 4.7 m f, esr = 0.5 w , v dd output capacitor c o = 4.7 m f, esr = 0.5 w , r bat <1 w . 2. this parameter is not tested during production; it is guaranteed by design. 3. this parameter depends on external components. 4. at high load or low battery voltage the inductor charge time can be extended to a full xtl1 period, while the minimum inductor discharge time is a half xtl1 period. 5. the execution time is strongly dependant on command type and addressing mode (see also table 60). zif (i and q) demodulator f offset offset from 0 frequency note 2 6 -- khz t (ena-avg) ena to valid avg value 3 khz offset; note 2 -- 100 ms t enb enb to valid demodulator output note 2 -- 1 symbol duration t enc enb to correct recovered clock note 2 phase error curves apply (see fig.27) all outputs t r,f rise and fall times for outputs c l =20pf - 15 - ns open-drain pins sda and scl (p1.7 and p1.6) t n noise suppression ?lter - 60 - ns d v/ d t slope for the falling edge r l =20k w ; c l = 50 pf; v dd = 2.2 v - 50 - ns/v di/dt slope for both edges r l =20k w ; c l =50pf - 250 -m a/ns i o(sink)(swl) dynamic output sink current during switching low (miller compensated) v dd = 2.2 v; r l =20k w ; c l =50pf - 2 - ma otp programming characteristics v su;pp v pp set-up time 10 --m s t w(prog) program pulse width 100 --m s t w(prog)(sec) program pulse security bits 200 --m s t w(prog)(rec) program pulse recover time 1 --m s afc-dac t start(dac) start-up time disabled dac to stable output for code 111111 note 2 - 50 100 m s psrr power supply ripple rejection (v dd -> dac) - 0 - db t slew slew time for analog output from 10 to 90% for a voltage step of 1 v code 010000 <-> 110000 - 2.5 -m s symbol parameter conditions min. typ. max. unit
1998 nov 02 87 philips semiconductors product speci?cation pager baseband controller pca5010 mgr161 ale psen variable execute time data input al driven data input ah driven ah driven p0 p2 3t 4t 5t 6t 0t 1t 2t 3t 4t 5t 6t .... nt sample p0 sample p0 ale, psen cycle t ce t instruction execution cycle fig.46 external access timing. t being the half period of the internal 6 mhz oscillator for normal external access and of tclk for emulation, programming and test modes. the minimum duration of one cycle is 6t. it can be extended by increments of [0 to n]t if the execution of an instruction needs more time (dependant of v dd , t, temperature, opcode). execution of an op-code goes in parallel with the external access cycle for the next sequential byte. eventually an already fetched byte is discarded depending on the executed instruction (e.g. any jump or return). 12 characteristic curves fig.47 measured battery current consumption as function of mean microcontroller instruction rate. handbook, full pagewidth 3 0 2 1 mgr144 (2) (1) 0 0.4 1.6 mips 2 1.2 0.8 i bat (ma) v bat = 1.2 v. (1) dc/dc converter in normal mode. (2) dc/dc converter in standby mode.
1998 nov 02 88 philips semiconductors product speci?cation pager baseband controller pca5010 fig.48 measured battery current consumption as function of mean microcontroller instruction rate. handbook, full pagewidth 0 0.4 1.6 mips 2 1.2 0.8 10 1 10 - 1 10 - 2 10 - 3 mgr145 (2) (3) (1) i bat (ma) v bat = 1.2 v. (1) dc/dc converter in normal mode. (2) dc/dc converter in standby mode. (3) dc/dc converter in off mode. fig.49 supply current in off mode. handbook, halfpage 0.8 1 1.2 1.6 10 0 8 mgr146 1.4 6 4 2 v bat (v) i bat ( m a) v dd =v bat , microcontroller idle, all functions disabled. fig.50 supply current in standby mode. handbook, halfpage 0.8 1 1.2 1.6 50 0 40 mgr147 1.4 30 20 10 v bat (v) i bat ( m a) v dd = 1.9 v, microcontroller idle, all functions disabled.
1998 nov 02 89 philips semiconductors product speci?cation pager baseband controller pca5010 fig.51 supply current in normal mode. v dd = 2.2 v, microcontroller idle, all functions disabled. note: this curve cannot be directly measured by varying v bat , because the shown current is the battery current in discontinuous mode. changing the battery voltage can force the dc/dc converter to enter continuous mode. at a given battery voltage a mode change from continuous to discontinuous mode happens only after a load reduction. handbook, halfpage 0.8 1 1.2 1.6 200 0 160 mgr148 1.4 120 80 40 v bat (v) i bat ( m a) fig.52 supply current in standby mode. v dd = 1.9 v, microcontroller running at approximately 1.6 mips, all other functions disabled. handbook, halfpage 3 1 0 2 mgr149 0.8 1 1.2 1.6 1.4 v bat (v) i bat (ma) fig.53 cpu speed performance with dc/dc in standby mode. v dd = 1.9 v, microcontroller running at maximum speed. handbook, halfpage 3 1 0 2 mgr150 0.8 1 1.2 1.6 1.4 v bat (v) mips
1998 nov 02 90 philips semiconductors product speci?cation pager baseband controller pca5010 fig.54 overall power/speed performance with dc/dc in standby mode. handbook, halfpage 0.8 1 1.2 1.6 1000 0 800 mgr349 1.4 600 400 200 v bat (v) mips/w v dd = 1.9 v, microcontroller running at maximum speed. fig.55 supply current in normal mode. handbook, halfpage 4 3 1 0 2 mgr152 0.8 1 1.2 1.6 1.4 v bat (v) i bat (ma) v dd = 2.2 v, microcontroller running at approximately 2 mips, all other functions disabled. fig.56 cpu speed performance with dc/dc converter in normal mode. v dd = 2.2 v, microcontroller running at maximum speed. handbook, halfpage 3 1 0 2 mgr153 0.8 1 1.2 1.6 1.4 v bat (v) mips fig.57 overall power/speed performance with dc/dc converter in normal mode. v dd = 2.2 v, microcontroller running at maximum speed. handbook, halfpage 800 600 200 0 400 mgr154 0.8 1 1.2 1.6 1.4 v bat (v) mips/w
1998 nov 02 91 philips semiconductors product speci?cation pager baseband controller pca5010 fig.58 speed performance pca5010 when v dd is externally supplied (dc/dc converter not used). handbook, halfpage 1.8 4 2 3 mips 1 0 2.2 3.8 mgr155 2.6 3 3.4 v dd (v) fig.59 typical impedance characteristic of standard port in input mode. handbook, halfpage 0 0.4 2 0 - 100 - 80 - 20 - 40 - 60 mgr156 1.2 0.8 2.4 1.6 i i ( m a) v i (v) pull-up current hold current fig.60 typical impedance characteristic of ea pin in input mode. handbook, halfpage 0 0.4 2 200 - 200 - 100 100 0 mgr157 1.2 0.8 2.4 1.6 v i (v) i i ( m a) fig.61 typical output characteristics driven high (digital output/port pins except p1.6 and p1.7). (1) pins p0.x, p1.x, p2.x, psen and ea. (2) pins resout and ale. (3) pins p3.x and at. handbook, halfpage 0 0.4 2.4 2 1.6 1.2 0 - 24 - 16 - 8 - 4 - 20 - 12 mgr158 0.8 v oh (v) i oh (ma) (2) (3) (1)
1998 nov 02 92 philips semiconductors product speci?cation pager baseband controller pca5010 fig.62 typical output characteristics low (digital output/port pins except p1.6 and p1.7). (1) pins p3.x and at. (2) pins resout and ale. (3) pins p0.x, p1.x, p2.x, psen and ea. handbook, halfpage 0 0.4 2.4 2 1.6 1.2 24 0 8 16 20 4 12 mgr159 0.8 v ol (v) i ol (ma) (2) (3) (1) fig.63 typical output characteristics low for p1.6 and p1.7. handbook, halfpage 0 0.4 2.4 2 1.6 1.2 24 0 8 16 20 4 12 mgr160 0.8 v o (v) i o (ma)
1998 nov 02 93 philips semiconductors product speci?cation pager baseband controller pca5010 13 test and application information fig.64 test circuit for current measurements with external v dd supply. handbook, full pagewidth mgr347 10 k w 2 m w 4.7 k w 4.7 k w 10 m f 4.7 m f v bat 76.8 khz v dd p3.3 48 p3.2 47 resout 46 resetin 45 v ss(dc) 44 vind 43 v dd(dc) 42 v bat 41 xtl1 40 xtl2 39 p1.7 38 p1.6 37 p0.1 13 p0.2 14 p0.3 15 p0.4 16 v dda 17 afcout 18 i(d1) 19 q(d0) 20 v ssa 21 p0.5 22 p0.6 23 p0.7 24 v pp 36 tclk 35 ea 34 psen 33 ale 32 p1.4 29 p1.3 28 p1.2 27 p1.1 26 p1.0 25 v dd 31 v ss 30 1 p3.5 2 p0.0 3 p3.4 at 4 p2.0 5 p2.3 8 p2.4 p2.1 p2.2 9 p2.5 10 p2.6 11 p2.7 12 6 7 PCA5010H v dd i dd i bat
1998 nov 02 94 philips semiconductors product speci?cation pager baseband controller pca5010 fig.65 test circuit for current measurements with on-chip dc/dc converter active. handbook, full pagewidth mgr348 10 k w 2 m w 4.7 k w 4.7 k w 10 m f 4.7 m f 470 m h v bat 76.8 khz v dd p3.3 48 p3.2 47 resout 46 resetin 45 v ss(dc) 44 vind 43 v dd(dc) 42 v bat 41 xtl1 40 xtl2 39 p1.7 38 p1.6 37 p0.1 13 p0.2 14 p0.3 15 p0.4 16 v dda 17 afcout 18 i(d1) 19 q(d0) 20 v ssa 21 p0.5 22 p0.6 23 p0.7 24 v pp 36 tclk 35 ea 34 psen 33 ale 32 p1.4 29 p1.3 28 p1.2 27 p1.1 26 p1.0 25 v dd 31 v ss 30 1 p3.5 2 p0.0 3 p3.4 at 4 p2.0 5 p2.3 8 p2.4 p2.1 p2.2 9 p2.5 10 p2.6 11 p2.7 12 6 7 PCA5010H
1998 nov 02 95 philips semiconductors product speci?cation pager baseband controller pca5010 14 appendix 1: special modes of the pca5010 14.1 overview during the rising edge of the external resout signal, the state of the pins ale, psen, ea and p2.x is sampled and stored. the following decoding (ale, psen and p2) is used to force the pca5010 into different operating modes: [1, 1, x] ? run mode [0, 1, x] ? emulation modes (for p2 decoding refer to metalink documents) [1, 0, y] ? test mode, submode y [0, 0, x] ? otp parallel programming mode. the customer will usually only see the normal run mode. 14.2 otp parallel programming mode the otp parallel programming mode is used to access the on-chip otp directly from the device pins for programming and verification. the otp parallel programming mode and its initialization are explained in detail in chapter 15. 14.3 test modes the test modes of the pca5010 are used during the production test of the circuit. test modes are not intended to be used by customers except test mode 2, the demodulator and clock recovery test mode. test mode 2 may be used by customers for ber measurements in closed-loop systems. the following application diagram (see fig.66) shows an application which enters this mode during start-up. after the test mode is entered the pca5010 starts execution of code from the internal program memory. this code must enable the demodulator and clock recovery in the required modes. if the microcontroller is requested to make port i/o, then a frequency of approximately 6 mhz with v dd level needs to be supplied at the tclk pin.
1998 nov 02 96 philips semiconductors product speci?cation pager baseband controller pca5010 fig.66 application diagram for entering the demodulator test mode after reset. the otp must contain code that enables the demodulator and clock recovery in the desired operating modes. handbook, full pagewidth mgr350 10 k w 2 m w 4.7 k w 4.7 k w 10 m f 76.8 khz p3.3 48 p3.2 47 resout 46 resetin 45 v ss(dc) 44 vind 43 v dd(dc) 42 v bat 41 xtl1 40 xtl2 39 p1.7 38 p1.6 37 p0.1 13 p0.2 14 p0.3 15 p0.4 16 v dda 17 afcout 18 i(d1) 19 q(d0) 20 v ssa 21 p0.5 22 p0.6 23 p0.7 24 v pp 36 tclk 35 ea 34 psen 33 ale 32 p1.4 29 p1.3 28 p1.2 27 p1.1 26 p1.0 25 v dd 31 v ss 30 1 p3.5 2 p0.0 3 p3.4 v bat at 4 p2.0 5 p2.3 8 p2.4 p2.1 p2.2 9 p2.5 10 p2.6 11 p2.7 12 6 7 PCA5010H 2.2 v recovered d1 recovered d0 2.2 k w i and q supplied from receiver 2.2 k w 2.2 k w 2.2 k w recovered symbol clock
1998 nov 02 97 philips semiconductors product speci?cation pager baseband controller pca5010 15 appendix 2: the parallel programming mode 15.1 introduction this document describes the parallel programming mode of the pca5010. parallel programming mode is the mode where the otp is programmed by an eprom programmer or by a tester. 15.2 general description the pca5010 is packaged in a lqfp48 package. port 0 and port 2 are available for programming. to program the otp of the pca5010, multiplexing of addresses and data is necessary. port 0 is a bidirectional data port, used for the memory addresses and the program and verify data. port 2 is an input port which controls the parallel programming mode. a coarse block diagram of the otp interface in parallel programming mode is given in fig.67. fig.67 the otp interface in parallel programming mode. handbook, full pagewidth mgr163 test control addl latch addh latch control logic p0 p2 otp interface parallel programming mode normal mode ctrl addr do (80c51) control do di add (otp) otpif
1998 nov 02 98 philips semiconductors product speci?cation pager baseband controller pca5010 15.2.1 s ignals for the parallel programming mode in this configuration, the following signals are necessary to program the otp: table 63 pins for programming mode the control signals gbmbpb, pgm, ls1 and ls0 can be used to select the latches of the interface block and the internal data latches of the otp. table 64 shows how the latches are selected. rdstrb is used to open the selected latch. if pgm is not active the rdstrb signal is used to start the otp read cycle. table 64 latch selection otp pin type eprom pin description comments v pp supply v pp programming voltage special pin/logic signal not time critical v dd supply v dd positive supply gnd supply gnd negative supply p0.7 to p0.0 io a<14:0> address 32 kbytes addresses available q<7:0> data-output i<7:0> data-input ps<2:0> security bits input connected to p0.2 to p0.0 pins qs<2:0> security bits output p2.0/ls0 input - latch select 0 latch select signals, see table 64 p2.1/ls1 input - latch select 1 p2.2/pgm input - programming mode p2.3/rdstrb input cep/mbpc read/strobe read enable clock (cep) when pgm = 0; strobe for the latches when pgm = 1 p2.4/gbmbpb input gb output enable not/ mult.bprog not read eprom and set p0 as output; multiple byte programming when pgm = 1 p2.5/web input web write enable not programs data if v pp is present p2.6/sec input sec select security bits see section 15.10 p2.7/sig input sig read signature bytes see section 15.9 p2.4/gbmbpb p2.2/pgm p2.1/ls1 p2.1/ls0 description x 0 x x no latches selected 1 1 0 0 select test control latch x 1 0 1 select lower address latch x 1 1 0 select upper address latch 0 1 1 1 select internal data latch in multi byte programming mode
1998 nov 02 99 philips semiconductors product speci?cation pager baseband controller pca5010 fig.68 parallel programming mode. handbook, full pagewidth mgr351 programmer ls0 addl/addh/data i/o ls1 pca5010 p2.0 p0.0 to p0.7 p2.1 pgm p2.2 rdstrb p2.3 gbmbpb p2.4 web p2.5 sig p2.6 sec p2.7 min psen mout2 ale mout1 ea resetn resetin clock tclk, xtl1 v dd v dd , v dda , v dd(dc) , v bat v ss v ss , v ssa , v ss(dc) v pp v pp 15.3 entering the parallel programming mode the parallel programming mode has been implemented as a general test mode of the pca5010. this mode can be entered by applying 000 to pins psen, ale, and ea during reset. for the initializing sequence a clock of 76.8 khz at xtl1 is expected and the supply voltage v dd must be higher then 2.2 v. at the rising edge of resout these signals are latched and the code 000 leads to parallel programming mode. the high voltage pin v pp can be either high or v dd . since psen and ale are output signals of the pca5010 after reset, a pull-down (strong enough to overdrive the internal 100 m a pull-up of the pca5010) should be used to drive the outputs low. alternatively the low can be driven with a 3-state buffer which is enabled with resout = low. the microcontroller fetches instructions from port 0 in external mode. data fetching is controlled by psen and ale. this is the standard data fetch in external mode. a clock has to be supplied to tclk while entering the parallel programming mode. before entering the parallel programming mode, port 2 should be set to 30h and the microcontroller should be put in idle mode by setting the bit pcon.0 (address 87h). the test mode is activated by making ea equal to logic 1. the mode entering sequence is given in table 65. before entering the parallel program mode port 2 can be an output port (dependent on the reset configuration of this port). as soon as the parallel programmed mode is entered port 2 is an input. after entering the parallel programming mode this mode has to be initialized. the otp test latch has to be loaded with code 01h to set the sense amplifiers in verify mode. before a byte can be programmed a verify has to be performed to check if programming is not blocked by the security (see section 15.10). the address of this verify cycle is not important and the address latches do not have to be loaded. after this initialization the pca5010 is ready for programming. parallel program initialization is shown in fig.71. the security check can be replaced by another read action e.g reading the security or signature bytes (see section 15.9). it should be noted that this paragraph is only applicable for the first series. it can be neglected in the future. to prevent problems with the self timed loop it is advised to set the circuit in dc read mode during verify. this is achieved by writing 09h instead of 01h into the otp test latch.
1998 nov 02 100 philips semiconductors product speci?cation pager baseband controller pca5010 table 65 entering the parallel programming mode; note 1 note 1. z = pin is output. pins psen, ale and ea resetin resout port 0 description 000 1 0 xx reset 000 0 0 xx 259 or more slow clocks at xtl1 000 0 0 ? 1 xx prepare parallel programming mode, enter external access mode, now clocks must be provided on tclk zz0 0 1 02 ljmp 3000h zz0 0 1 30 force p2 to 30h zz0 0 1 00 zz0 0 1 00 discard fetch cycle zz0 0 1 75 mov pcon, 01h zz0 0 1 87 make microcontroller idle zz0 0 1 01 zz0 0 1 01 discard fetch cycle zz1 0 1 xx parallel programming mode active h mgr165 ale psen variable execute time data input al driven data input ah driven ah driven p0 p2 3t 4t 5t 6t 0t 1t 2t 3t 4t 5t 6t .... nt sample p0 sample p0 ale, psen cycle t ce t instruction execution cycle fig.69 external access timing for programming mode entry. t being the half period of the clock signal supplied to tclk. the minimum duration of one cycle is 6t. it can be extended by increments of [0 to n]t if the execution of an instruction needs more time (dependant of v dd , t, temperature, opcode). execution of an op-code goes in parallel with the external access cycle for the next sequential byte. eventually an already fetched byte is discarded depending on the executed instruction (e.g. any jump or return).
1998 nov 02 101 philips semiconductors product speci?cation pager baseband controller pca5010 fig.70 program mode entry. handbook, full pagewidth mgr166 p2 p0 psen ale ea resout resetin minimum 259 clocks on xtl1 (f < 100 khz) 30 00 00 00 00 30 30 30 30 xx 02 01 87 75 xx 00 30 dummy fetch cycles, will be discarded clocking on tclk (1) (f = 500 khz) mode entry microcontroller idle parallel programming mode ale, psen latched see fig.8. fig.71 parallel program mode initialization. handbook, full pagewidth mgr167 v pp p0.7 to p0.0 p2.1/ls0 p2.0/ls1 p2.2/pgm p2.3/rdstrb p2.5/web 01h xx set verify mode check security initialization ready v dd = 12.5 to 13 v
1998 nov 02 102 philips semiconductors product speci?cation pager baseband controller pca5010 15.4 address space the pca5010 has a 32 kbytes memory and therefore 15 address pins. applying an address above 32 kbytes (address<15> = 1) leads to the selection of the extra rows. the user should not apply these addresses during programming. 15.5 single byte programming programming and verifying is shown in fig.72. the upper and lower address byte are loaded one after the other. the address latch control signals select the proper latch and the rdstrb signal opens the latch (level sensitive). the order of loading the latches is not important. the data is latched if write enable bar becomes active. after programming a byte, this byte can be verified without reloading the addresses. if more bytes are programmed after each other having the same upper address, it is not necessary to reload this upper address. fig.72 single byte programming mode. handbook, full pagewidth mgr168 v pp p0.0 to p0.7 p2.1/ls1 p2.0/ls0 p2.2/pgm p2.3/rdstrb p2.5/web p2.4/gbmbpb addr high addr low data in data out addr/data set-up program 100 m s verify v dd = 12.5 to 13 v 15.6 multiple byte programming a multiple byte programming mode has been implemented to increase programming speed. in this mode four bytes can be programmed in parallel. the addresses of these four bytes have to be equal except for bit 0 and bit 1. loading the address and data latches is enabled by making pgm high and gbmbpb low at the same time. figure 73 shows the address and data set-up and the program pulse. loading the upper address is only necessary if it differs from the upper address of the previous quadruple of bytes. in this mode the data latches are controlled by the rdstrb signal (level sensitive). figure 74 shows the verification in this mode. it should be noted that data 3 is verified before data 0. if this is unwanted the lower address byte of data 0 has to be loaded before verifying data 0 and the lower address byte of data 1 before verifying data 1.
1998 nov 02 103 philips semiconductors product speci?cation pager baseband controller pca5010 fig.73 multiple byte programming mode (address and data load, programming pulse). handbook, full pagewidth mgr169 v pp p0.0 to p0.7 p2.1/ll1 p2.0/ll0 p2.2/pgm p2.3/rdstrb p2.5/web p2.4/gbmbpb addr high addr lo0 addr lo1 di_0 di_1 addr lo2 di_2 addr lo3 di_3 addr/data_0 to data_1 set-up program v dd = 12.5 to 13 v fig.74 multiple byte programming mode (verify). handbook, full pagewidth mgr170 v pp p0.7 to p0.0 p2.1/ll0 p2.0/ll1 p2.2/pgm p2.3/rdstrb p2.5/web p2.4/gbmbpb addr lo2 addr lo1 do_2 do_3 do_1 addr lo0 do_0 verify v dd = 12.5 to 13 v
1998 nov 02 104 philips semiconductors product speci?cation pager baseband controller pca5010 15.7 high voltage timing the external program voltage v pp has to be high while a program pulse is applied (web active). during verify it can be either high or equal to the supply voltage. v pp has to be stable for at least 10 m s before a program pulse can be applied. after applying a program pulse a recover time of 1 m s is needed to discharge the internal high voltage nodes. during this recover time the memory cannot be accessed for verify. due to the above mentioned setup time programming time is reduced if v pp is continuously high during programming and verifying. 15.8 otp test modes otp test modes will be selected from a test control latch which can be loaded in parallel programming over port 0. the advantage of this is that the test modes of the otp are independent of the microcontroller. table 66 shows the otp test modes coded in 7 bits. when a test mode is loaded the control signals on port 2 keep their original functionality and can be used to execute the test mode. table 66 de?nition of test modes tcl(7 to 0) test mode 00000000 normal mode (no test active) xxxxxx01 verify mode (self timed) xxxxxx10 margin 0 mode xxxxxx11 margin 1 mode xxxxx1xx margin vp mode is active xxxx1xxx dc_read mode is active x001xxxx drain stress test mode x010xxxx gate stress test mode x011xxxx mass programming test mode x100xxxx even column test mode x101xxxx odd column test mode x110xxxx even row test mode x111xxxx odd row test mode 1xxxxxxx otp interface test the encoding is such that combinations of test modes are possible, for instance tcb(7 to 0) = 00001100 enables both the margin vp and dc_read test modes. the so called vt mode, needed to measure analog cell characteristics, can be entered by making both p2.6/sig and p2.7/sec active. during normal programming this mode should not be entered therefore it is forbidden to make p2.6/sig and p2.7/sec high at the same time . 15.8.1 m ass program mode the mass program mode can be used to program checker boards. if this mode is active every internal data latch is connected to four bit lines and 128 bits can be programmed in parallel. to write a checker board 0011x0xx has to be loaded in the test register and the circuit has to be set in parallel program mode (p2.2/pgm = 1 and p2.4/gbmbpb = 0). then data from address 00h is loaded to address 00 03h down to 00 00h. for every even word line (a<6> = 0) a program pulse has to be given at low addresses x0000000 and x0001000. for the odd lines (a<6> = 1) the pulses have to be applied to low address x1000100 and x1001100. in the user address space a checker board can be programmed with 320 2 = 640 program pulses. 15.9 signature bytes three signature bytes are available to identify the device. these bytes can be read by doing a verify while the sig input (port 2.6) is active. the contents of the signature bytes is given in table 67. applying a write pulse while the sig input is high is forbidden although the contents of the signature bytes will never be destroyed. the signature bytes are always readable independent on the security. table 67 addresses and contents of the signature bytes address contents 00 30h 15h 00 31h d9h 00 60h h0h
1998 nov 02 105 philips semiconductors product speci?cation pager baseband controller pca5010 15.10 security to prevent programming or reading of eprom contents by third parties security can be set by programming the security bits. these bits are located outside the normal memory matrix and have input and output lines separated from the normal otp i/os. three bits are present, but only two are actually used. the third bit can be used for future extensions. different levels of security can be set by programming one or more bits. the bits are read in parallel at every read cycle and interpreted with the following definition: level 0, bits 000, no security, no restrictions level 1, bits 001, program disabled level 2, bits 011, program and verify disabled. the third security may be programmed without affecting the functionality. however only the combinations 000, 001, 011 and 111 are possible. after reset security level 1 is loaded. to enable programming a read or verify (gb pulse not necessary) is needed to check the actual security level. the security bits can be programmed the same as normal bits. the bits have to be supplied to the three least significant bits of port 0. the sec bit of port 2 (bit 7) has to be high during the program cycle. loading an address is not necessary. if port 2.7/sec is high during verify, the security bits can be read on the three least significant bits of port 0. after programming 011 to the security bits only the security bits and the signature bytes can be verified and verifying the normal addresses is not possible any more. verifying a normal address while security level 2 has been programmed will result in reading 00h. the programming time for the security bits is 200 m s instead of 100 m s for a normal bit. this extra time can be reached by applying one 200 m s program pulse or by applying two standard pulses. although in this otp an unprogrammed cell is a logic 1 and a programmed cell is a logic 0, a logic 1 has to be programmed to increase the security level. the inversion is performed by the interface block. since the security is checked at every read or verify access, verifying is disabled immediately after programming security level 2. programming is disabled if a verify or a reset is applied after programming security level 1 or higher.
1998 nov 02 106 philips semiconductors product speci?cation pager baseband controller pca5010 16 appendix 3: os sheet fig.75 open/short-circuit diagram for pca5010. handbook, full pagewidth mgr171 v pp v pp v bat substrate v ss tclk ea psen v dd v dd v ss p1.4 p1.3 p1.2 p1.1 p1.0 ale resout resetin v ss(dc) vind v dd(dc) xtl1 xtl2 p1.7 p1.6 v bat p3.4 p3.5 at p2.0 p2.1 p2.2 p2.4 p2.5 p2.7 p0.0 p2.3 p2.6 p0.2 p0.3 p0.4 v dda afcout i(d1) q(d0) p0.5 p0.6 p0.7 p0.1 v ssa p3.3 p3.2 36 35 34 33 32 31 30 29 28 27 26 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1
1998 nov 02 107 philips semiconductors product speci?cation pager baseband controller pca5010 17 appendix 4: bonding pad locations table 68 bonding pad locations (dimensions in m m) pad name bond pin centre x bond pin centre y pad size x, y 1 p3.4 91.0 3930.0 87.0 2 p3.5 91.0 3770.0 87.0 3 at 91.0 3600.0 87.0 4 p2.0 91.0 3430.0 87.0 5 p2.1 91.0 3260.0 87.0 6 p2.2 91.0 3090.0 87.0 7 p2.3 91.0 1240.0 87.0 8 p2.4 91.0 1060.0 87.0 9 p2.5 91.0 880.0 87.0 fig.76 bonding pad locations. handbook, full pagewidth mgr352 1 48 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 2 3 4 5 6 7 8 9 10 11 12 30 31 32 33 34 35 36 29 28 27 26 25 pca5010 4.06 mm 4.44 mm
1998 nov 02 108 philips semiconductors product speci?cation pager baseband controller pca5010 10 p2.6 91.0 700.0 87.0 11 p2.7 91.0 520.0 87.0 12 p0.0 91.0 340.0 87.0 13 p0.1 420.0 91.0 87.0 14 p0.2 630.0 91.0 87.0 15 p0.3 842.0 91.0 87.0 16 p0.4 1055.0 91.0 87.0 17 v dda 2170.0 91.0 87.0 18 afcout 2392.5 91.0 87.0 19 i(d1) 2595.0 91.0 87.0 20 q(d0) 2795.0 91.0 87.0 21 v ssa 2997.5 91.0 87.0 22 p0.5 3195.0 91.0 87.0 23 p0.6 3392.5 91.0 87.0 24 p0.7 3590.0 91.0 87.0 25 p1.0 3827.2 410.0 87.0 26 p1.1 3827.2 620.0 87.0 27 p1.2 3827.2 830.0 87.0 28 p1.3 3 827.2 1040.0 87.0 29 p1.4 3827.2 1217.5 87.0 30 v ss 3827.2 1377.5 87.0 31 v dd 3827.2 2417.5 87.0 32 ale 3827.2 2580.0 87.0 33 psen 3827.2 2890.0 87.0 34 ea 3827.2 3200.0 87.0 35 tclk 3827.2 3510.0 87.0 36 v pp 3827.2 3820.0 87.0 37 p1.6 3383.1 4231.5 87.0 38 p1.7 3079.6 4231.5 87.0 39 xtl2 2743.4 4231.5 87.0 40 xtl1 2364.1 4231.5 87.0 41 v bat 1964.5 4231.5 87.0 42 powerpads 1550.0 4231.5 84.0 43 powerpads 1310.0 4231.5 84.0 44 powerpads 1190.0 4231.5 87.0 45 resetin 953.2 4231.5 87.0 46 resout 766.2 4231.5 87.0 47 p3.2 579.2 4231.5 87.0 48 p3.3 392.2 4231.5 87.0 pad name bond pin centre x bond pin centre y pad size x, y
1998 nov 02 109 philips semiconductors product speci?cation pager baseband controller pca5010 18 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 94-12-19 97-08-01 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
1998 nov 02 110 philips semiconductors product speci?cation pager baseband controller pca5010 19 soldering 19.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). 19.2 re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. 19.3 wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all lqfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for lqfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 nov 02 111 philips semiconductors product speci?cation pager baseband controller pca5010 20 definitions 21 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 22 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. 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novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 435102/00/01/pp112 date of release: 1998 nov 02 document order number: 9397 750 03988

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